c986a3d520
Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
140 lines
5.9 KiB
C
140 lines
5.9 KiB
C
/****************************************************************************/
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/*
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* m5272sim.h -- ColdFire 5272 System Integration Module support.
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*
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef m5272sim_h
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#define m5272sim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m5272)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK MCF_CLK
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#include <asm/m52xxacr.h>
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/*
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* Define the 5272 SIM register set addresses.
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*/
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#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
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#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
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#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
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#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
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#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
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#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
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#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
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#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
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#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
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#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
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#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
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#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
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#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
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#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
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#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
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#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
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#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
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#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
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#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
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#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
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#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
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#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
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#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
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#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
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#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
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#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
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#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
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#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
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#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
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#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
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#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
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#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
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#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
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#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
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#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
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#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
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#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
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#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
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#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
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#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
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#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
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#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
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#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
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#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
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#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
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#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
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#define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */
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#define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */
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#define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */
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#define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */
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#define MCFFEC_SIZE0 0x1d0
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCFINT_VECBASE 64 /* Base of interrupts */
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#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
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#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
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#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
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#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
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#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
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#define MCF_IRQ_TIMER1 69 /* Timer 1 */
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#define MCF_IRQ_TIMER2 70 /* Timer 2 */
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#define MCF_IRQ_TIMER3 71 /* Timer 3 */
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#define MCF_IRQ_TIMER4 72 /* Timer 4 */
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#define MCF_IRQ_UART0 73 /* UART 0 */
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#define MCF_IRQ_UART1 74 /* UART 1 */
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#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
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#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
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#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
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#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
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#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
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#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
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#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
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#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
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#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
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#define MCF_IRQ_DMA 85 /* DMA Controller */
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#define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */
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#define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */
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#define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */
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#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
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#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
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#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
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#define MCF_IRQ_SWTO 92 /* Software Watchdog */
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#define MCFINT_VECMAX 95 /* Maxmum interrupt */
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#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
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#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PIN_MAX 48
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#define MCFGPIO_IRQ_MAX -1
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#define MCFGPIO_IRQ_VECBASE -1
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/****************************************************************************/
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#endif /* m5272sim_h */
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