c9dff05030
Add the GPIO I/O memory range to the r8a7790 PFC device. This extra I/O memory range is needed when using the PFC tables to drive both pin functions (using PINCTRL or function GPIO for old code) and actual GPIO. The goal is however to use a separate GPIO driver in the long run and when that happens this extra I/O memory range can be removed. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
/*
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* r8a7790 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/serial_sci.h>
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#include <linux/platform_data/irq-renesas-irqc.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <mach/r8a7790.h>
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#include <asm/mach/arch.h>
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static const struct resource pfc_resources[] = {
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DEFINE_RES_MEM(0xe6060000, 0x250),
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DEFINE_RES_MEM(0xe6050000, 0x5050),
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};
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void __init r8a7790_pinmux_init(void)
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{
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platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
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ARRAY_SIZE(pfc_resources));
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}
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#define SCIF_COMMON(scif_type, baseaddr, irq) \
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.type = scif_type, \
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.mapbase = baseaddr, \
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.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
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.irqs = SCIx_IRQ_MUXED(irq)
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#define SCIFA_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
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}
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#define SCIFB_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_4, \
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.scscr = SCSCR_RE | SCSCR_TE, \
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}
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#define SCIF_DATA(index, baseaddr, irq) \
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[index] = { \
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SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
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.scbrr_algo_id = SCBRR_ALGO_2, \
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.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
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}
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enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
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static const struct plat_sci_port scif[] = {
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SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
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SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
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SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
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SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
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SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
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SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
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SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
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SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
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};
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static inline void r8a7790_register_scif(int idx)
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{
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platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
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sizeof(struct plat_sci_port));
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}
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static struct renesas_irqc_config irqc0_data = {
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.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
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};
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static struct resource irqc0_resources[] = {
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DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
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DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
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DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
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DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
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DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
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};
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#define r8a7790_register_irqc(idx) \
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platform_device_register_resndata(&platform_bus, "renesas_irqc", \
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idx, irqc##idx##_resources, \
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ARRAY_SIZE(irqc##idx##_resources), \
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&irqc##idx##_data, \
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sizeof(struct renesas_irqc_config))
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void __init r8a7790_add_standard_devices(void)
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{
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r8a7790_register_scif(SCIFA0);
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r8a7790_register_scif(SCIFA1);
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r8a7790_register_scif(SCIFB0);
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r8a7790_register_scif(SCIFB1);
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r8a7790_register_scif(SCIFB2);
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r8a7790_register_scif(SCIFA2);
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r8a7790_register_scif(SCIF0);
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r8a7790_register_scif(SCIF1);
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r8a7790_register_irqc(0);
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}
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#ifdef CONFIG_USE_OF
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void __init r8a7790_add_standard_devices_dt(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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static const char *r8a7790_boards_compat_dt[] __initdata = {
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"renesas,r8a7790",
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NULL,
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};
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DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
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.init_irq = irqchip_init,
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.init_machine = r8a7790_add_standard_devices_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a7790_boards_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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