Roger Quadros c9f9eba066 phy: ti: j721e-wiz: Manage typec-gpio-dir ... Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>		2020-01-14 10:50:19 +05:30
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Kconfig	phy: Enable compile testing for some of drivers	2020-01-14 10:50:19 +05:30
Makefile	phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC	2020-01-14 10:50:19 +05:30
phy-am654-serdes.c	We have a small collection of core framework updates this time, mostly around	2019-09-20 15:45:07 -07:00
phy-da8xx-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	2019-06-05 17:36:37 +02:00
phy-dm816x-usb.c	phy: ti: dm816x: remove set but not used variable 'phy_data'	2019-10-25 17:58:13 +05:30
phy-gmii-sel.c	phy: ti: gmii-sel: fix mac tx internal delay for rgmii-rxid	2019-10-25 17:58:15 +05:30
phy-j721e-wiz.c	phy: ti: j721e-wiz: Manage typec-gpio-dir	2020-01-14 10:50:19 +05:30
phy-omap-control.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
phy-omap-usb2.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	2019-05-30 11:26:37 -07:00
phy-ti-pipe3.c	phy: ti-pipe3: make clk operations symmetric in probe and remove	2019-12-20 17:00:45 +05:30
phy-tusb1210.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
phy-twl4030-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 61	2019-05-24 17:36:45 +02:00