4dc49062a7
When utilizing PARSE_SFDP to initialize the flash parameter, the
deprecated initializing method spi_nor_init_params_deprecated() and the
function spi_nor_manufacturer_init_params() within it will never be
executed, which results in the default_init hook function will also never
be executed.
This is okay for 'D' generation of GD25Q256, because 'D' generation is
implementing the JESD216B standards, it has QER field defined in BFPT,
parsing the SFDP can properly set the quad_enable function. The 'E'
generation also implements the JESD216B standards, and it has the same
status register definitions as 'D' generation, parsing the SFDP to set
the quad_enable function should also work for 'E' generation.
However, the same thing can't apply to 'C' generation. 'C' generation
'GD25Q256C' implements the JESD216 standards, and it doesn't have the
QER field defined in BFPT, since it does have QE bit in status register
1, the quad_enable hook needs to be tweaked to properly set the
quad_enable function, this can be done in post_bfpt fixup hook.
Fixes: 047275f7de ("mtd: spi-nor: gigadevice: gd25q256: Init flash based on SFDP")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Yaliang Wang <Yaliang.Wang@windriver.com>
[tudor.ambarus@microchip.com: Update comment in gd25q256_post_bfpt]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20221016171901.1483542-2-yaliang.wang@windriver.com
77 lines
2.6 KiB
C
77 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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static int
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gd25q256_post_bfpt(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt)
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{
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/*
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* GD25Q256C supports the first version of JESD216 which does not define
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* the Quad Enable methods. Overwrite the default Quad Enable method.
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*
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* GD25Q256 GENERATION | SFDP MAJOR VERSION | SFDP MINOR VERSION
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* GD25Q256C | SFDP_JESD216_MAJOR | SFDP_JESD216_MINOR
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* GD25Q256D | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
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* GD25Q256E | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
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*/
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if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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bfpt_header->minor == SFDP_JESD216_MINOR)
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nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
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return 0;
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}
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static const struct spi_nor_fixups gd25q256_fixups = {
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.post_bfpt = gd25q256_post_bfpt,
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};
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static const struct flash_info gigadevice_nor_parts[] = {
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{ "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256)
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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SPI_NOR_QUAD_READ) },
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{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512)
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PARSE_SFDP
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FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
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FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
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.fixups = &gd25q256_fixups },
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};
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const struct spi_nor_manufacturer spi_nor_gigadevice = {
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.name = "gigadevice",
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.parts = gigadevice_nor_parts,
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.nparts = ARRAY_SIZE(gigadevice_nor_parts),
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};
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