ca8b387803
On newer r-car SoCs the CHCLR register only contains one bit per channel, to which a 1 has to be written to reset the channel. Older SoC versions had one CHCLR register per channel, to which a 0 must be written to reset the channel and clear its buffers. This patch adds support for the newer layout. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| shdma-base.c | ||
| shdma-of.c | ||
| shdma.c | ||
| shdma.h | ||
| sudmac.c | ||