cd1e64935f
The ISA states: "when ACC[i] contains defined data, the contents of VSRs
4×i to 4×i+3 are undefined until either a VSX Move From ACC instruction
is used to copy the contents of ACC[i] to VSRs 4×i to 4×i+3 or some other
instruction directly writes to one of these VSRs." We aren't doing this.
This test only works on Power10 because the hardware implementation
happens to map ACC0 to VSRs 0-3, but will fail on any other implementation
that doesn't do this. So add xxmfacc between writing to the accumulator
and accessing the VSRs.
Fixes: 3527e1ab9a79 ("selftests/powerpc: Add matrix multiply assist (MMA) test")
Signed-off-by: Rashmica Gupta <rashmica@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220617043935.428083-1-rashmica@linux.ibm.com
37 lines
761 B
ArmAsm
37 lines
761 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Test basic matrix multiply assist (MMA) functionality if available.
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*
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* Copyright 2020, Alistair Popple, IBM Corp.
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*/
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.global test_mma
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test_mma:
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/* Load accumulator via VSX registers from image passed in r3 */
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lxvh8x 4,0,3
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lxvh8x 5,0,4
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/* Clear and prime the accumulator (xxsetaccz) */
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.long 0x7c030162
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/* Prime the accumulator with MMA VSX move to accumulator
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* X-form (xxmtacc) (not needed due to above zeroing) */
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//.long 0x7c010162
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/* xvi16ger2s */
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.long 0xec042958
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/* Deprime the accumulator - xxmfacc 0 */
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.long 0x7c000162
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/* Store result in image passed in r5 */
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stxvw4x 0,0,5
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addi 5,5,16
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stxvw4x 1,0,5
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addi 5,5,16
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stxvw4x 2,0,5
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addi 5,5,16
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stxvw4x 3,0,5
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addi 5,5,16
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blr
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