IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
- Icache is 2-way set associative
- Dcache is 4-way set associative
- L2cache is 16-way set associative
- Line size are 64bytes
Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.
So add the cache info in device tree and let use could see that
from /sys/devices/system/cpu/cpu[x]/cache/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
cb551b5e3b