Peter De Schrijver cbfc8d0a85 clk: tegra: add fence_delay for clock registers ...

To ensure writes to clock registers have properly propagated through the
clock control logic and state machines, we need to ensure the writes have
been posted in the registers and wait for 1us after that.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Hector Martin <marcan@marcan.st>
Tested-by: Andre Heider <a.heider@gmail.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

2018-03-08 15:26:54 +01:00

..

clk-audio-sync.c

clk: tegra: Remove CLK_IS_ROOT

2016-03-02 17:47:19 -08:00

clk-bpmp.c

clk: tegra: Check BPMP response return code

2017-10-19 16:38:40 +02:00

clk-dfll.c

clk: tegra: dfll: Fix drvdata overwriting issue

2017-11-01 15:00:06 +01:00

clk-dfll.h

clk: tegra: dfll: Fix drvdata overwriting issue

2017-11-01 15:00:06 +01:00

clk-divider.c

tegra/clk-divider: fix wrong do_div() usage

2015-11-16 12:37:55 -05:00

clk-emc.c

clk: Convert to using %pOF instead of full_name

2017-07-21 15:49:54 -07:00

clk-id.h

We have two changes to the core framework this time around. The first being a

2017-11-17 20:04:24 -08:00

clk-periph-fixed.c

clk: tegra: Add fixed factor peripheral clock type

2016-04-28 12:41:47 +02:00

clk-periph-gate.c

clk: tegra: Fix disable unused for clocks sharing enable bit

2017-03-20 14:13:52 +01:00

clk-periph.c

clk: tegra: Add peripheral clock registration helper

2017-10-19 16:38:40 +02:00

clk-pll-out.c

clk: tegra: Properly include clk.h

2015-07-20 11:11:17 -07:00

clk-pll.c

clk: tegra: Fix T210 PLLRE registration

2017-08-23 16:00:23 -07:00

clk-super.c

clk: tegra: Add super clock mux/divider

2017-03-20 14:07:33 +01:00

clk-tegra20.c

clk: tegra: Bump SCLK clock rate to 216 MHz

2017-11-01 15:00:05 +01:00

clk-tegra30.c

clk: tegra: Fix cclk_lp divisor register

2017-11-01 15:00:06 +01:00

clk-tegra114.c

clk: tegra: Use tegra_clk_register_periph_data()

2017-10-19 16:38:41 +02:00

clk-tegra124-dfll-fcpu.c

clk: tegra: dfll: Fix drvdata overwriting issue

2017-11-01 15:00:06 +01:00

clk-tegra124.c

clk: tegra: Add CEC clock

2017-03-20 14:06:23 +01:00

clk-tegra210.c

clk: tegra: Add la clock for Tegra210

2018-03-08 15:26:11 +01:00

clk-tegra-audio.c

clk: tegra: Define Tegra210 DMIC sync clocks

2017-03-20 14:06:33 +01:00

clk-tegra-fixed.c

clk: tegra: Remove trailing blank line

2016-04-28 12:41:45 +02:00

clk-tegra-periph.c

clk: tegra: Correct parent of the APBDMA clock

2017-11-01 15:00:04 +01:00

clk-tegra-pmc.c

clk: tegra: Propagate clk_out_x rate to parent

2017-04-04 16:00:28 +02:00

clk-tegra-super-gen4.c

clk: tegra: Mark APB clock as critical

2017-11-01 14:58:13 +01:00

clk.c

clk: tegra: Implement reset control reset

2017-03-20 14:15:31 +01:00

clk.h

clk: tegra: add fence_delay for clock registers

2018-03-08 15:26:54 +01:00

cvb.c

clk: tegra: dfll: improve function-level documentation

2016-11-01 17:38:50 -07:00

cvb.h

clk: tegra: dfll: Properly clean up on failure and removal

2016-04-28 12:41:54 +02:00

Kconfig

clk: tegra: Add BPMP clock driver

2017-02-03 12:36:36 -08:00

Makefile

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

2017-11-02 11:10:55 +01:00