47e794d69c
PIPE_MBUS_DBOX_CTL was only being programmed when a pipe is being enabled but that could potentially cause issues as it could have mismatching values while pipes are being enabled. So here moving the PIPE_MBUS_DBOX_CTL programming of all pipes to be executed before the function that enables all pipes, leaving all pipes with a matching A_CREDIT value. While at it, also moving it to intel_pm.c as we are trying to reduce the gigantic size of intel_display.c and intel_pm.c have other MBUS programing sequences. v2: - do not program PIPE_MBUS_DBOX_CTL if pipe will not be active or when it do not needs modeset - remove the checks to wait a vblank v3: - checking if dbuf state is present in state before using it v4: - removing redundant checks - calling intel_atomic_get_new_dbuf_state instead of intel_atomic_get_dbuf_state BSpec: 49213 BSpec: 50343 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220330155724.255226-3-jose.souza@intel.com
100 lines
3.8 KiB
C
100 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_PM_H__
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#define __INTEL_PM_H__
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#include <linux/types.h>
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#include "display/intel_display.h"
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#include "display/intel_global_state.h"
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#include "i915_drv.h"
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struct drm_device;
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struct drm_i915_private;
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struct i915_request;
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struct intel_atomic_state;
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struct intel_bw_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_plane;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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void intel_init_clock_gating(struct drm_i915_private *dev_priv);
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void intel_suspend_hw(struct drm_i915_private *dev_priv);
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int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
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void intel_init_pm(struct drm_i915_private *dev_priv);
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
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void intel_pm_setup(struct drm_i915_private *dev_priv);
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void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
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void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
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u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
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void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
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struct skl_ddb_entry *ddb_y,
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struct skl_ddb_entry *ddb_uv);
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
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u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
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const struct skl_ddb_entry *entry);
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void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
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struct skl_pipe_wm *out);
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void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
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void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
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void skl_wm_sanitize(struct drm_i915_private *dev_priv);
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bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
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const struct intel_bw_state *bw_state);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
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enum plane_id plane_id,
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int level);
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const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
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enum plane_id plane_id);
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bool skl_wm_level_equals(const struct skl_wm_level *l1,
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const struct skl_wm_level *l2);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void skl_write_plane_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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void skl_write_cursor_wm(struct intel_plane *plane,
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const struct intel_crtc_state *crtc_state);
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bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
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void intel_init_ipc(struct drm_i915_private *dev_priv);
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void intel_enable_ipc(struct drm_i915_private *dev_priv);
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bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
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struct intel_dbuf_state {
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struct intel_global_state base;
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struct skl_ddb_entry ddb[I915_MAX_PIPES];
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unsigned int weight[I915_MAX_PIPES];
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u8 slices[I915_MAX_PIPES];
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u8 enabled_slices;
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u8 active_pipes;
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bool joined_mbus;
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};
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
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#define intel_atomic_get_old_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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#define intel_atomic_get_new_dbuf_state(state) \
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to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
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int intel_dbuf_init(struct drm_i915_private *dev_priv);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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void intel_mbus_dbox_update(struct intel_atomic_state *state);
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#endif /* __INTEL_PM_H__ */
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