7158780169
We found out that we are unable to control the PERST# signal via the
default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
value of this register does not change the pin output when measuring
with voltmeter.
We do not know if this is a bug in the SOC, or if it works only when
PCIe controller is in a certain state.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready
before training link") says that when this pin changes pinctrl mode
from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
moment.
So currently the situation is that on A3700 boards the PERST# signal is
asserted in U-Boot (because the code in U-Boot issues reset via this pin
via GPIO mode), and then in Linux by the obscure and undocumented
mechanism described by the above mentioned commit.
We want to issue PERST# signal in a known way, therefore this patch
changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
reset-gpios property to the PCIe node in device tree files of
EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
has this property and uDPU does not have a PCIe port).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Remi Pommarel <repk@triplefau.lt>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
221 lines
4.3 KiB
Plaintext
221 lines
4.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for Marvell Armada 3720 development board
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* (DB-88F3720-DDR3)
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is compatible with the version 1.4 and the version 2.0 of
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* the board, however the CON numbers are different between the 2
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* version
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-372x.dtsi"
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/ {
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model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
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};
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exp_usb3_vbus: usb3-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb3-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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regulator-always-on;
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gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
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};
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usb3_phy: usb3-phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <&exp_usb3_vbus>;
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};
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vcc_sd_reg1: regulator {
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compatible = "regulator-gpio";
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regulator-name = "vcc_sd1";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
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gpios-states = <0>;
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states = <1800000 0x1
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3300000 0x0>;
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enable-active-high;
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};
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vcc_sd_reg2: regulator-vmcc {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sd2";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>;
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};
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};
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/* Gigabit module on CON19(V2.0)/CON21(V1.4) */
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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phy-mode = "rgmii-id";
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phy = <&phy0>;
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status = "okay";
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};
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/* Gigabit module on CON18(V2.0)/CON20(V1.4) */
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ð1 {
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phy-mode = "sgmii";
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phy = <&phy1>;
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status = "okay";
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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status = "okay";
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gpio_exp: pca9555@22 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x22>;
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/*
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* IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT
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* IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE
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* IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN
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* IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN
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* IO0_4: PWR_EN_SD
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* IO0_5: PWR_EN_EMMC
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* IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL
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* IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS
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*/
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};
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rtc@68 {
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/* PT7C4337A from pericom fully compatible with the ds1337 */
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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&mdio {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
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reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* CON3 */
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&sata {
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status = "okay";
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};
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&sdhci0 {
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non-removable;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs400-1_8v;
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marvell,pad-type = "fixed-1-8v";
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status = "okay";
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};
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/* SD slot module on CON14(V2.0)/CON15(V1.4) */
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&sdhci1 {
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wp-inverted;
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cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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marvell,pad-type = "sd";
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vqmmc-supply = <&vcc_sd_reg1>;
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vmmc-supply = <&vcc_sd_reg2>;
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status = "okay";
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};
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&spi0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi_quad_pins>;
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m25p80@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <108000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0x0 0x200000>;
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};
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partition@200000 {
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label = "U-boot Env";
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reg = <0x200000 0x10000>;
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};
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partition@210000 {
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label = "Linux";
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reg = <0x210000 0xDF0000>;
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};
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};
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};
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};
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/*
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* Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through
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* an FTDI (also on CON24(V2.0)/CON26(V1.4)).
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*/
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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/* CON26(V2.0)/CON28(V1.4) */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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/* CON27(V2.0)/CON29(V1.4) */
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&usb2 {
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status = "okay";
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};
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/* CON29(V2.0)/CON31(V1.4) */
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&usb3 {
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status = "okay";
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usb-phy = <&usb3_phy>;
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};
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