6485fc18fa
AMD systems from Renoir and Lucienne require that the NVME controller is put into D3 over a Modern Standby / suspend-to-idle cycle. This is "typically" accomplished using the `StorageD3Enable` property in the _DSD, but this property was introduced after many of these systems launched and most OEM systems don't have it in their BIOS. On AMD Renoir without these drives going into D3 over suspend-to-idle the resume will fail with the NVME controller being reset and a trace like this in the kernel logs: ``` [ 83.556118] nvme nvme0: I/O 161 QID 2 timeout, aborting [ 83.556178] nvme nvme0: I/O 162 QID 2 timeout, aborting [ 83.556187] nvme nvme0: I/O 163 QID 2 timeout, aborting [ 83.556196] nvme nvme0: I/O 164 QID 2 timeout, aborting [ 95.332114] nvme nvme0: I/O 25 QID 0 timeout, reset controller [ 95.332843] nvme nvme0: Abort status: 0x371 [ 95.332852] nvme nvme0: Abort status: 0x371 [ 95.332856] nvme nvme0: Abort status: 0x371 [ 95.332859] nvme nvme0: Abort status: 0x371 [ 95.332909] PM: dpm_run_callback(): pci_pm_resume+0x0/0xe0 returns -16 [ 95.332936] nvme 0000:03:00.0: PM: failed to resume async: error -16 ``` The Microsoft documentation for StorageD3Enable mentioned that Windows has a hardcoded allowlist for D3 support, which was used for these platforms. Introduce quirks to hardcode them for Linux as well. As this property is now "standardized", OEM systems using AMD Cezanne and newer APU's have adopted this property, and quirks like this should not be necessary. CC: Shyam-sundar S-k <Shyam-sundar.S-k@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Prike Liang <prike.liang@amd.com> Link: https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Julian Sikorski <belegdol@gmail.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
163 lines
5.4 KiB
C
163 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* X86 ACPI Utility Functions
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*
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* Copyright (C) 2017 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on various non upstream patches to support the CHT Whiskey Cove PMIC:
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* Copyright (C) 2013-2015 Intel Corporation. All rights reserved.
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*/
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include "../internal.h"
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/*
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* Some ACPI devices are hidden (status == 0x0) in recent BIOS-es because
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* some recent Windows drivers bind to one device but poke at multiple
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* devices at the same time, so the others get hidden.
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*
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* Some BIOS-es (temporarily) hide specific APCI devices to work around Windows
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* driver bugs. We use DMI matching to match known cases of this.
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*
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* We work around this by always reporting ACPI_STA_DEFAULT for these
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* devices. Note this MUST only be done for devices where this is safe.
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*
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* This forcing of devices to be present is limited to specific CPU (SoC)
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* models both to avoid potentially causing trouble on other models and
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* because some HIDs are re-used on different SoCs for completely
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* different devices.
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*/
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struct always_present_id {
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struct acpi_device_id hid[2];
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struct x86_cpu_id cpu_ids[2];
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struct dmi_system_id dmi_ids[2]; /* Optional */
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const char *uid;
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};
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#define X86_MATCH(model) X86_MATCH_INTEL_FAM6_MODEL(model, NULL)
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#define ENTRY(hid, uid, cpu_models, dmi...) { \
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{ { hid, }, {} }, \
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{ cpu_models, {} }, \
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{ { .matches = dmi }, {} }, \
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uid, \
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}
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static const struct always_present_id always_present_ids[] = {
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/*
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* Bay / Cherry Trail PWM directly poked by GPU driver in win10,
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* but Linux uses a separate PWM driver, harmless if not used.
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*/
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ENTRY("80860F09", "1", X86_MATCH(ATOM_SILVERMONT), {}),
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ENTRY("80862288", "1", X86_MATCH(ATOM_AIRMONT), {}),
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/* Lenovo Yoga Book uses PWM2 for keyboard backlight control */
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ENTRY("80862289", "2", X86_MATCH(ATOM_AIRMONT), {
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DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X9"),
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}),
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/*
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* The INT0002 device is necessary to clear wakeup interrupt sources
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* on Cherry Trail devices, without it we get nobody cared IRQ msgs.
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*/
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ENTRY("INT0002", "1", X86_MATCH(ATOM_AIRMONT), {}),
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/*
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* On the Dell Venue 11 Pro 7130 and 7139, the DSDT hides
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* the touchscreen ACPI device until a certain time
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* after _SB.PCI0.GFX0.LCD.LCD1._ON gets called has passed
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* *and* _STA has been called at least 3 times since.
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*/
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ENTRY("SYNA7500", "1", X86_MATCH(HASWELL_L), {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7130"),
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}),
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ENTRY("SYNA7500", "1", X86_MATCH(HASWELL_L), {
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DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME, "Venue 11 Pro 7139"),
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}),
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/*
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* The GPD win BIOS dated 20170221 has disabled the accelerometer, the
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* drivers sometimes cause crashes under Windows and this is how the
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* manufacturer has solved this :| Note that the the DMI data is less
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* generic then it seems, a board_vendor of "AMI Corporation" is quite
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* rare and a board_name of "Default String" also is rare.
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*
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* Unfortunately the GPD pocket also uses these strings and its BIOS
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* was copy-pasted from the GPD win, so it has a disabled KIOX000A
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* node which we should not enable, thus we also check the BIOS date.
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*/
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ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "02/21/2017")
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}),
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ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "03/20/2017")
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}),
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ENTRY("KIOX000A", "1", X86_MATCH(ATOM_AIRMONT), {
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DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
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DMI_MATCH(DMI_BOARD_NAME, "Default string"),
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DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
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DMI_MATCH(DMI_BIOS_DATE, "05/25/2017")
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}),
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};
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bool acpi_device_always_present(struct acpi_device *adev)
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{
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bool ret = false;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(always_present_ids); i++) {
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if (acpi_match_device_ids(adev, always_present_ids[i].hid))
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continue;
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if (!adev->pnp.unique_id ||
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strcmp(adev->pnp.unique_id, always_present_ids[i].uid))
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continue;
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if (!x86_match_cpu(always_present_ids[i].cpu_ids))
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continue;
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if (always_present_ids[i].dmi_ids[0].matches[0].slot &&
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!dmi_check_system(always_present_ids[i].dmi_ids))
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continue;
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ret = true;
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break;
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}
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return ret;
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}
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/*
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* AMD systems from Renoir and Lucienne *require* that the NVME controller
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* is put into D3 over a Modern Standby / suspend-to-idle cycle.
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*
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* This is "typically" accomplished using the `StorageD3Enable`
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* property in the _DSD that is checked via the `acpi_storage_d3` function
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* but this property was introduced after many of these systems launched
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* and most OEM systems don't have it in their BIOS.
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*
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* The Microsoft documentation for StorageD3Enable mentioned that Windows has
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* a hardcoded allowlist for D3 support, which was used for these platforms.
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*
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* This allows quirking on Linux in a similar fashion.
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*/
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static const struct x86_cpu_id storage_d3_cpu_ids[] = {
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /* Renoir */
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X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104, NULL), /* Lucienne */
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{}
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};
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bool force_storage_d3(void)
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{
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return x86_match_cpu(storage_d3_cpu_ids);
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}
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