eb4733d7cf
There are several issues which may be seen when the link goes down while
forwarding traffic, all of which can be attributed to the fact that the
port flushing procedure from the reference manual was not closely
followed.
With flow control enabled on both the ingress port and the egress port,
it may happen when a link goes down that Ethernet packets are in flight.
In flow control mode, frames are held back and not dropped. When there
is enough traffic in flight (example: iperf3 TCP), then the ingress port
might enter congestion and never exit that state. This is a problem,
because it is the egress port's link that went down, and that has caused
the inability of the ingress port to send packets to any other port.
This is solved by flushing the egress port's queues when it goes down.
There is also a problem when performing stream splitting for
IEEE 802.1CB traffic (not yet upstream, but a sort of multicast,
basically). There, if one port from the destination ports mask goes
down, splitting the stream towards the other destinations will no longer
be performed. This can be traced down to this line:
ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);
which should have been instead, as per the reference manual:
ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
DEV_MAC_ENA_CFG);
Basically only DEV_MAC_ENA_CFG_RX_ENA should be disabled, but not
DEV_MAC_ENA_CFG_TX_ENA - I don't have further insight into why that is
the case, but apparently multicasting to several ports will cause issues
if at least one of them doesn't have DEV_MAC_ENA_CFG_TX_ENA set.
I am not sure what the state of the Ocelot VSC7514 driver is, but
probably not as bad as Felix/Seville, since VSC7514 uses phylib and has
the following in ocelot_adjust_link:
if (!phydev->link)
return;
therefore the port is not really put down when the link is lost, unlike
the DSA drivers which use .phylink_mac_link_down for that.
Nonetheless, I put ocelot_port_flush() in the common ocelot.c because it
needs to access some registers from drivers/net/ethernet/mscc/ocelot_rew.h
which are not exported in include/soc/mscc/ and a bugfix patch should
probably not move headers around.
Fixes: bdeced75b13f ("net: dsa: felix: Add PCS operations for PHYLINK")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
152 lines
3.4 KiB
C
152 lines
3.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include "ocelot.h"
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u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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u32 val;
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WARN_ON(!target);
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regmap_read(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, &val);
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return val;
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}
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EXPORT_SYMBOL(__ocelot_read_ix);
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void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_write(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, val);
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}
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EXPORT_SYMBOL(__ocelot_write_ix);
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void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
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u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_update_bits(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset,
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mask, val);
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}
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EXPORT_SYMBOL(__ocelot_rmw_ix);
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u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
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{
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struct ocelot *ocelot = port->ocelot;
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u16 target = reg >> TARGET_OFFSET;
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u32 val;
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WARN_ON(!target);
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regmap_read(port->target, ocelot->map[target][reg & REG_MASK], &val);
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return val;
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}
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EXPORT_SYMBOL(ocelot_port_readl);
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void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg)
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{
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struct ocelot *ocelot = port->ocelot;
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_write(port->target, ocelot->map[target][reg & REG_MASK], val);
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}
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EXPORT_SYMBOL(ocelot_port_writel);
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void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask, u32 reg)
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{
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u32 cur = ocelot_port_readl(port, reg);
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ocelot_port_writel(port, (cur & (~mask)) | val, reg);
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}
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EXPORT_SYMBOL(ocelot_port_rmwl);
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u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
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u32 reg, u32 offset)
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{
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u32 val;
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regmap_read(ocelot->targets[target],
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ocelot->map[target][reg] + offset, &val);
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return val;
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}
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void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
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u32 val, u32 reg, u32 offset)
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{
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regmap_write(ocelot->targets[target],
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ocelot->map[target][reg] + offset, val);
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}
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int ocelot_regfields_init(struct ocelot *ocelot,
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const struct reg_field *const regfields)
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{
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unsigned int i;
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u16 target;
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for (i = 0; i < REGFIELD_MAX; i++) {
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struct reg_field regfield = {};
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u32 reg = regfields[i].reg;
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if (!reg)
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continue;
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target = regfields[i].reg >> TARGET_OFFSET;
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regfield.reg = ocelot->map[target][reg & REG_MASK];
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regfield.lsb = regfields[i].lsb;
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regfield.msb = regfields[i].msb;
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regfield.id_size = regfields[i].id_size;
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regfield.id_offset = regfields[i].id_offset;
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ocelot->regfields[i] =
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devm_regmap_field_alloc(ocelot->dev,
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ocelot->targets[target],
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regfield);
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if (IS_ERR(ocelot->regfields[i]))
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return PTR_ERR(ocelot->regfields[i]);
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_regfields_init);
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static struct regmap_config ocelot_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res)
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{
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void __iomem *regs;
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regs = devm_ioremap_resource(ocelot->dev, res);
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if (IS_ERR(regs))
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return ERR_CAST(regs);
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ocelot_regmap_config.name = res->name;
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return devm_regmap_init_mmio(ocelot->dev, regs, &ocelot_regmap_config);
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}
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EXPORT_SYMBOL(ocelot_regmap_init);
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