Yash Shah cfda8617e2 riscv: dts: Add DT support for SiFive L2 cache controller ... Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2020-01-03 00:56:23 -08:00
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boot	riscv: dts: Add DT support for SiFive L2 cache controller	2020-01-03 00:56:23 -08:00
configs	Merge branch 'next/defconfig-add-debug' into for-next	2019-11-22 18:59:23 -08:00
include	riscv: define vmemmap before pfn_to_page calls	2019-12-20 03:32:24 -08:00
kernel	riscv: reject invalid syscalls below -1	2019-12-27 21:50:57 -08:00
lib	riscv: fix compile failure with EXPORT_SYMBOL() & !MMU	2019-12-27 21:44:36 -08:00
mm	riscv: mm: use __pa_symbol for kernel symbols	2020-01-03 00:33:34 -08:00
net	bpf, riscv: Limit to 33 tail calls	2019-12-11 13:57:17 +01:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: gcov: enable gcov for RISC-V	2020-01-03 00:47:02 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: only select serial sifive if TTY is enabled	2019-12-08 20:29:01 -08:00
Makefile	riscv: provide a flat image loader	2019-11-17 15:17:39 -08:00