Vignesh R d087f15786 dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63
Register layout of a typical TPCC_EVT_MUX_M_N register is such that the
lowest numbered event is at the lowest byte address and highest numbered
event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is
different,  in that the lowest numbered event is at the highest address
and highest numbered event is at the lowest address. Therefore, modify
ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register
accordingly.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-12-22 17:48:07 +05:30
..
2017-11-14 16:49:31 -08:00
2017-11-14 16:49:31 -08:00
2016-03-24 23:13:48 -07:00
2017-11-14 16:49:31 -08:00
2016-09-05 16:40:52 +05:30
2017-01-25 15:33:45 +05:30