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Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 32 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.531157061@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
96 lines
2.3 KiB
C
96 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* Defines of the Malta board specific address-MAP, registers, etc.
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*/
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#ifndef __ASM_MIPS_BOARDS_MALTA_H
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#define __ASM_MIPS_BOARDS_MALTA_H
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/gt64120.h>
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/* Mips interrupt controller found in SOCit variations */
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#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
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#define MIPS_SOCITSC_IC_REG_BASE 0x1ffa0000
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/*
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* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
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* Bonito system controllers.
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*/
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#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
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#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
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#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
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static inline unsigned long get_gt_port_base(unsigned long reg)
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{
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unsigned long addr;
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addr = GT_READ(reg);
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return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
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}
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static inline unsigned long get_msc_port_base(unsigned long reg)
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{
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unsigned long addr;
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MSC_READ(reg, addr);
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return (unsigned long) ioremap(addr, 0x10000);
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}
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/*
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* GCMP Specific definitions
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*/
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#define GCMP_BASE_ADDR 0x1fbf8000
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#define GCMP_ADDRSPACE_SZ (256 * 1024)
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/*
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* GIC Specific definitions
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*/
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#define GIC_BASE_ADDR 0x1bdc0000
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#define GIC_ADDRSPACE_SZ (128 * 1024)
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/*
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* CPC Specific definitions
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*/
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#define CPC_BASE_ADDR 0x1bde0000
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/*
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* MSC01 BIU Specific definitions
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* FIXME : These should be elsewhere ?
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*/
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#define MSC01_BIU_REG_BASE 0x1bc80000
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#define MSC01_BIU_ADDRSPACE_SZ (256 * 1024)
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#define MSC01_SC_CFG_OFS 0x0110
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#define MSC01_SC_CFG_GICPRES_MSK 0x00000004
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#define MSC01_SC_CFG_GICPRES_SHF 2
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#define MSC01_SC_CFG_GICENA_SHF 3
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/*
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* Malta RTC-device indirect register access.
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*/
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#define MALTA_RTC_ADR_REG 0x70
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#define MALTA_RTC_DAT_REG 0x71
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/*
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* Malta SMSC FDC37M817 Super I/O Controller register.
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*/
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#define SMSC_CONFIG_REG 0x3f0
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#define SMSC_DATA_REG 0x3f1
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#define SMSC_CONFIG_DEVNUM 0x7
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#define SMSC_CONFIG_ACTIVATE 0x30
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#define SMSC_CONFIG_ENTER 0x55
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#define SMSC_CONFIG_EXIT 0xaa
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#define SMSC_CONFIG_DEVNUM_FLOPPY 0
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#define SMSC_CONFIG_ACTIVATE_ENABLE 1
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#define SMSC_WRITE(x, a) outb(x, a)
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#define MALTA_JMPRS_REG 0x1f000210
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#endif /* __ASM_MIPS_BOARDS_MALTA_H */
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