Masahiro Yamada 955d809bde ARM: tegra: Remove redundant ARM_L1_CACHE_SHIFT_6 select
These two are both ARMv7 SoCs.  They need not explicitly select
ARM_L1_CACHE_SHIFT_6 because it is enabled along with CPU_V7.

Refer to commit a092f2b15399 ("ARM: 7291/1: cache: assume 64-byte L1
cachelines for ARMv7 CPUs").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-12 17:09:28 +02:00
..
2016-03-19 15:38:41 -07:00
2016-01-22 17:26:00 -08:00