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linux/drivers/clk/renesas
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Biju Das d1c20885d3 clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write 
As per the RZ/G2L HW(Rev.1.30 May2023) manual, there are no "write enable"
bits in the CPG_SIPLL5_CLK1 register.  So fix the CPG_SIPLL5_CLK register
write by removing the "write enable" bits.

Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230518152334.514922-1-biju.das.jz@bp.renesas.com
[geert: Remove CPG_SIPLL5_CLK1_*_WEN bit definitions]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-23 09:06:50 +02:00
..
clk-div6.c
clk: renesas: div6: Implement range checking
2021-05-11 09:58:13 +02:00
clk-div6.h
We have two changes to the core framework this time around. The first being a
2017-11-17 20:04:24 -08:00
clk-emev2.c
Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next
2018-10-18 15:33:52 -07:00
clk-mstp.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
clk-r8a73a4.c
clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7740.c
clk: renesas: r8a7740: Remove r8a7740_cpg.reg
2022-06-13 11:53:18 +02:00
clk-r8a7778.c
clk: renesas: r8a7778: Remove struct r8a7778_cpg
2022-06-13 11:53:18 +02:00
clk-r8a7779.c
clk: renesas: r8a7779: Remove struct r8a7779_cpg
2022-06-13 11:53:18 +02:00
clk-rz.c
clk: renesas: rza1: Remove struct rz_cpg
2022-06-13 11:53:18 +02:00
clk-sh73a0.c
clk: renesas: sh73a0: Remove sh73a0_cpg.reg
2022-06-13 11:53:18 +02:00
Kconfig
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2023-02-10 10:35:16 +01:00
Makefile
clk: renesas: Add RZ/V2M support using the rzg2l driver
2022-05-06 09:38:40 +02:00
r7s9210-cpg-mssr.c
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a774b1-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a774c0-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a774e1-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a779a0-cpg-mssr.c
clk: renesas: r8a779a0: Add PWM clock
2023-05-08 09:14:33 +02:00
r8a779f0-cpg-mssr.c
clk: renesas: r8a779f0: Fix Ethernet Switch clocks
2022-11-16 09:05:59 +01:00
r8a779g0-cpg-mssr.c
clk: renesas: r8a779g0: Add VIN clocks
2023-03-06 10:42:14 +01:00
r8a7742-cpg-mssr.c
clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-04 09:42:01 +02:00
r8a7743-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2023-02-10 10:35:16 +01:00
r8a7796-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a77470-cpg-mssr.c
clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)
2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a77970-cpg-mssr.c
clk: renesas: r8a77970: Add Z2 clock
2023-03-10 17:07:07 +01:00
r8a77980-cpg-mssr.c
clk: renesas: r8a77980: Add I2C5 clock
2023-03-30 16:44:04 +02:00
r8a77990-cpg-mssr.c
clk: renesas: Move RPC core clocks
2022-04-13 12:27:45 +02:00
r8a77995-cpg-mssr.c
clk: renesas: r8a77995: Fix VIN parent clock
2023-03-06 10:42:14 +01:00
r9a06g032-clocks.c
clk: renesas: r9a06g032: Improve clock tables
2023-03-10 17:09:00 +01:00
r9a07g043-cpg.c
clk: renesas: r9a07g043: Drop WDT2 clock and reset entry
2022-10-26 12:38:01 +02:00
r9a07g044-cpg.c
clk: renesas: r9a07g044: Add clock and reset entries for CRU
2023-01-12 17:18:48 +01:00
r9a09g011-cpg.c
clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
2022-12-27 09:45:23 +01:00
rcar-cpg-lib.c
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-cpg-lib.h
clk: renesas: rcar-gen3: Switch to new SD clock handling
2021-11-19 11:32:39 +01:00
rcar-gen2-cpg.c
clk: renesas: Zero init clk_init_data
2021-03-30 09:58:27 +02:00
rcar-gen2-cpg.h
clk: renesas: rcar-gen2: Change multipliers and dividers to u8
2019-12-10 10:24:10 +01:00
rcar-gen3-cpg.c
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2023-02-10 10:35:16 +01:00
rcar-gen3-cpg.h
clk: renesas: r8a77995: Add RPC clocks
2022-04-11 12:13:13 +02:00
rcar-gen4-cpg.c
clk: renesas: r8a779g0: Add custom clock for PLL2
2023-01-24 10:11:50 +01:00
rcar-gen4-cpg.h
clk: renesas: r8a779g0: Add custom clock for PLL2
2023-01-24 10:11:50 +01:00
rcar-usb2-clock-sel.c
clk: renesas: Convert to platform remove callback returning void
2023-03-16 16:54:21 +01:00
renesas-cpg-mssr.c
Nothing looks out of the ordinary in this batch of clk driver updates. There
2023-04-29 17:29:39 -07:00
renesas-cpg-mssr.h
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
2023-02-10 10:35:16 +01:00
rzg2l-cpg.c
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
2023-05-23 09:06:50 +02:00
rzg2l-cpg.h
clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
2023-05-23 09:06:50 +02:00