6ebd9a4f8b
Update the test_ctl_hi_val and test_ctl_hi1_val of gpu_cc_pll1
as per latest HW recommendation.
Fixes: 0cef71f2cc ("clk: qcom: Add graphics clock controller driver for SM8150")
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231122042814.4158076-1-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
332 lines
7.9 KiB
C
332 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/module.h>
|
|
#include <linux/platform_device.h>
|
|
#include <linux/regmap.h>
|
|
|
|
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
|
|
|
|
#include "common.h"
|
|
#include "clk-alpha-pll.h"
|
|
#include "clk-branch.h"
|
|
#include "clk-pll.h"
|
|
#include "clk-rcg.h"
|
|
#include "clk-regmap.h"
|
|
#include "reset.h"
|
|
#include "gdsc.h"
|
|
|
|
enum {
|
|
P_BI_TCXO,
|
|
P_GPLL0_OUT_MAIN,
|
|
P_GPLL0_OUT_MAIN_DIV,
|
|
P_GPU_CC_PLL1_OUT_MAIN,
|
|
};
|
|
|
|
static const struct pll_vco trion_vco[] = {
|
|
{ 249600000, 2000000000, 0 },
|
|
};
|
|
|
|
static struct alpha_pll_config gpu_cc_pll1_config = {
|
|
.l = 0x1a,
|
|
.alpha = 0xaaa,
|
|
.config_ctl_val = 0x20485699,
|
|
.config_ctl_hi_val = 0x00002267,
|
|
.config_ctl_hi1_val = 0x00000024,
|
|
.test_ctl_val = 0x00000000,
|
|
.test_ctl_hi_val = 0x00000000,
|
|
.test_ctl_hi1_val = 0x00000020,
|
|
.user_ctl_val = 0x00000000,
|
|
.user_ctl_hi_val = 0x00000805,
|
|
.user_ctl_hi1_val = 0x000000d0,
|
|
};
|
|
|
|
static struct clk_alpha_pll gpu_cc_pll1 = {
|
|
.offset = 0x100,
|
|
.vco_table = trion_vco,
|
|
.num_vco = ARRAY_SIZE(trion_vco),
|
|
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_pll1",
|
|
.parent_data = &(const struct clk_parent_data){
|
|
.fw_name = "bi_tcxo",
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_alpha_pll_trion_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static const struct parent_map gpu_cc_parent_map_0[] = {
|
|
{ P_BI_TCXO, 0 },
|
|
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
|
|
{ P_GPLL0_OUT_MAIN, 5 },
|
|
{ P_GPLL0_OUT_MAIN_DIV, 6 },
|
|
};
|
|
|
|
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
|
|
{ .fw_name = "bi_tcxo" },
|
|
{ .hw = &gpu_cc_pll1.clkr.hw },
|
|
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
|
|
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
|
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sc8180x[] = {
|
|
F(19200000, P_BI_TCXO, 1, 0, 0),
|
|
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
|
|
F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
|
|
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
|
|
.cmd_rcgr = 0x1120,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = gpu_cc_parent_map_0,
|
|
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
|
|
.clkr.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_gmu_clk_src",
|
|
.parent_data = gpu_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_ahb_clk = {
|
|
.halt_reg = 0x1078,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x1078,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_crc_ahb_clk = {
|
|
.halt_reg = 0x107c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x107c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_crc_ahb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_cx_apb_clk = {
|
|
.halt_reg = 0x1088,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1088,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_cx_apb_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_cx_gmu_clk = {
|
|
.halt_reg = 0x1098,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1098,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_cx_gmu_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&gpu_cc_gmu_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
|
|
.halt_reg = 0x108c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x108c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_cx_snoc_dvm_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_cxo_aon_clk = {
|
|
.halt_reg = 0x1004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_cxo_aon_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_cxo_clk = {
|
|
.halt_reg = 0x109c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x109c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_cxo_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch gpu_cc_gx_gmu_clk = {
|
|
.halt_reg = 0x1064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "gpu_cc_gx_gmu_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&gpu_cc_gmu_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc gpu_cx_gdsc = {
|
|
.gdscr = 0x106c,
|
|
.gds_hw_ctrl = 0x1540,
|
|
.pd = {
|
|
.name = "gpu_cx_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = VOTABLE,
|
|
};
|
|
|
|
static struct gdsc gpu_gx_gdsc = {
|
|
.gdscr = 0x100c,
|
|
.clamp_io_ctrl = 0x1508,
|
|
.pd = {
|
|
.name = "gpu_gx_gdsc",
|
|
.power_on = gdsc_gx_do_nothing_enable,
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
|
|
};
|
|
|
|
static struct clk_regmap *gpu_cc_sm8150_clocks[] = {
|
|
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
|
|
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
|
|
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
|
|
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
|
|
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
|
|
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
|
|
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
|
|
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
|
|
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
|
|
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map gpu_cc_sm8150_resets[] = {
|
|
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
|
|
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
|
|
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
|
|
[GPUCC_GPU_CC_SPDM_BCR] = { 0x1110 },
|
|
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
|
|
};
|
|
|
|
static struct gdsc *gpu_cc_sm8150_gdscs[] = {
|
|
[GPU_CX_GDSC] = &gpu_cx_gdsc,
|
|
[GPU_GX_GDSC] = &gpu_gx_gdsc,
|
|
};
|
|
|
|
static const struct regmap_config gpu_cc_sm8150_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x8008,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc gpu_cc_sm8150_desc = {
|
|
.config = &gpu_cc_sm8150_regmap_config,
|
|
.clks = gpu_cc_sm8150_clocks,
|
|
.num_clks = ARRAY_SIZE(gpu_cc_sm8150_clocks),
|
|
.resets = gpu_cc_sm8150_resets,
|
|
.num_resets = ARRAY_SIZE(gpu_cc_sm8150_resets),
|
|
.gdscs = gpu_cc_sm8150_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8150_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id gpu_cc_sm8150_match_table[] = {
|
|
{ .compatible = "qcom,sc8180x-gpucc" },
|
|
{ .compatible = "qcom,sm8150-gpucc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, gpu_cc_sm8150_match_table);
|
|
|
|
static int gpu_cc_sm8150_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &gpu_cc_sm8150_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-gpucc"))
|
|
gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sc8180x;
|
|
|
|
clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
|
|
|
|
return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver gpu_cc_sm8150_driver = {
|
|
.probe = gpu_cc_sm8150_probe,
|
|
.driver = {
|
|
.name = "sm8150-gpucc",
|
|
.of_match_table = gpu_cc_sm8150_match_table,
|
|
},
|
|
};
|
|
|
|
static int __init gpu_cc_sm8150_init(void)
|
|
{
|
|
return platform_driver_register(&gpu_cc_sm8150_driver);
|
|
}
|
|
subsys_initcall(gpu_cc_sm8150_init);
|
|
|
|
static void __exit gpu_cc_sm8150_exit(void)
|
|
{
|
|
platform_driver_unregister(&gpu_cc_sm8150_driver);
|
|
}
|
|
module_exit(gpu_cc_sm8150_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI GPUCC SM8150 Driver");
|
|
MODULE_LICENSE("GPL v2");
|