2aa0d4c881
There is no need to specify "minItems" if it equals to "maxItems". On the other hand number of items in an array can be specified via describing items, which might bring some additional information. This simplifies a bit the binding. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220712154602.26994-1-krzysztof.kozlowski@linaro.org
145 lines
3.7 KiB
YAML
145 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
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maintainers:
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- Michael Srba <Michael.Srba@seznam.cz>
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description: |
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This binding describes the dependencies (clocks, resets, power domains) which
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need to be turned on in a sequence before communication over the AHB bus
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becomes possible.
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Additionally, the reg property is used to pass to the driver the location of
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two sadly undocumented registers which need to be poked as part of the sequence.
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The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
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controllers, a hexagon core, and a clock controller which provides clocks for
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the above.
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properties:
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compatible:
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items:
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- const: qcom,msm8998-ssc-block-bus
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- const: qcom,ssc-block-bus
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reg:
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items:
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- description: SSCAON_CONFIG0 registers
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- description: SSCAON_CONFIG1 registers
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reg-names:
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items:
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- const: mpm_sscaon_config0
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- const: mpm_sscaon_config1
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'#address-cells':
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enum: [ 1, 2 ]
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'#size-cells':
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enum: [ 1, 2 ]
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ranges: true
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clocks:
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maxItems: 6
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clock-names:
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items:
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- const: xo
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- const: aggre2
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- const: gcc_im_sleep
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- const: aggre2_north
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- const: ssc_xo
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- const: ssc_ahbs
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power-domains:
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items:
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- description: CX power domain
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- description: MX power domain
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power-domain-names:
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items:
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- const: ssc_cx
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- const: ssc_mx
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resets:
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items:
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- description: Main reset
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- description:
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SSC Branch Control Register reset (associated with the ssc_xo and
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ssc_ahbs clocks)
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reset-names:
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items:
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- const: ssc_reset
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- const: ssc_bcr
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qcom,halt-regs:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: describes how to locate the ssc AXI halt register
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items:
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- items:
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- description: Phandle reference to a syscon representing TCSR
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- description: offset for the ssc AXI halt register
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required:
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- compatible
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- reg
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- reg-names
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- '#address-cells'
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- '#size-cells'
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- ranges
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- clocks
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- clock-names
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- power-domains
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- power-domain-names
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- resets
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- reset-names
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- qcom,halt-regs
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additionalProperties:
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type: object
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8998.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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// devices under this node are physically located in the SSC block, connected to an ssc-internal bus;
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ssc_ahb_slave: bus@10ac008 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
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reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
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reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
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clocks = <&xo>,
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<&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
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<&gcc GCC_IM_SLEEP>,
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<&gcc AGGRE2_SNOC_NORTH_AXI>,
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<&gcc SSC_XO>,
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<&gcc SSC_CNOC_AHBS_CLK>;
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clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
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resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>;
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reset-names = "ssc_reset", "ssc_bcr";
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power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
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power-domain-names = "ssc_cx", "ssc_mx";
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qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
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};
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};
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