b34ae8598c
On SM8550, two sets of UFS PHY settings are provided, one set is to support HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY settings are programming different values to different registers, mixing the two sets and/or overwriting one set with another set is definitely not blessed by UFS PHY designers. To add HS-G5 support for SM8550, split the two sets of PHY settings into their dedicated overlay tables, only the common parts of the two sets of PHY settings are left in the .tbls. Consider we are going to add even higher gear support in future, to avoid adding more tables with different names, rename the .tbls_hs_g4 and make it an array, a size of 2 is enough as of now. In this case, .tbls alone is not a complete set of PHY settings, so either tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the .tbls to become a complete set of PHY settings. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Can Guo <quic_cang@quicinc.com> Link: https://lore.kernel.org/r/1703557892-1822-1-git-send-email-quic_cang@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
35 lines
1.3 KiB
C
35 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
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#define QCOM_PHY_QMP_PCS_UFS_V6_H_
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/* Only for QMP V6 PHY - UFS PCS registers */
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#define QPHY_V6_PCS_UFS_PHY_START 0x000
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#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V6_PCS_UFS_SW_RESET 0x008
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020
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#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
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#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
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#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
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#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
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#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
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#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
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#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
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#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
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#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
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#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
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#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
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#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
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#endif
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