0ba37e05c2
This patch adds basic arch initialization and instruction associate
support for the riscv64 CPU architecture.
Example output:
$ perf annotate --stdio2
Samples: 122K of event 'task-clock:u', 4000 Hz, Event count (approx.): 30637250000, [percent: local period]
strcmp() /usr/lib64/libc-2.32.so
Percent
Disassembly of section .text:
0000000000069a30 <strcmp>:
__GI_strcmp():
const unsigned char *s2 = (const unsigned char *) p2;
unsigned char c1, c2;
do
{
c1 = (unsigned char) *s1++;
37.30 lbu a5,0(a0)
c2 = (unsigned char) *s2++;
1.23 addi a1,a1,1
c1 = (unsigned char) *s1++;
18.68 addi a0,a0,1
c2 = (unsigned char) *s2++;
1.37 lbu a4,-1(a1)
if (c1 == '\0')
18.71 ↓ beqz a5,18
return c1 - c2;
}
Signed-off-by: William Cohen <wcohen@redhat.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-riscv@lists.infradead.org
Link: http://lore.kernel.org/lkml/20210927005115.610264-1-wcohen@redhat.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
35 lines
726 B
C
35 lines
726 B
C
// SPDX-License-Identifier: GPL-2.0
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static
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struct ins_ops *riscv64__associate_ins_ops(struct arch *arch, const char *name)
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{
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struct ins_ops *ops = NULL;
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if (!strncmp(name, "jal", 3) ||
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!strncmp(name, "jr", 2) ||
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!strncmp(name, "call", 4))
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ops = &call_ops;
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else if (!strncmp(name, "ret", 3))
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ops = &ret_ops;
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else if (name[0] == 'j' || name[0] == 'b')
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ops = &jump_ops;
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else
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return NULL;
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arch__associate_ins_ops(arch, name, ops);
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return ops;
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}
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static
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int riscv64__annotate_init(struct arch *arch, char *cpuid __maybe_unused)
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{
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if (!arch->initialized) {
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arch->associate_instruction_ops = riscv64__associate_ins_ops;
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arch->initialized = true;
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arch->objdump.comment_char = '#';
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}
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return 0;
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}
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