Vineet Gupta d4599baf5c ARC: cacheflush optim - PTAG can be loop invariant if V-P is const ... Line op needs vaddr (indexing) and paddr (tag match). For page sized flushes (V-P const), each line op will need a different index, but the tag bits wil remain constant, hence paddr can be setup once outside the loop. This improves select LMBench numbers for Aliasing dcache where we have more "preventive" cache flushing. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 3.11-rc7- Linux 3.11.0- 80 4.66 8.88 69.7 112. 268. 8.60 28.0 3489 13.K 27.K # Non alias ARC700 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 68.6 98.5 271. 8.58 28.1 4160 15.K 32.K # Aliasing 3.11-rc7- Linux 3.11.0- 80 4.64 8.51 69.8 99.4 270. 8.73 27.5 3880 15.K 31.K # PTAG loop Inv Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2013-11-06 10:41:38 +05:30
..
cache_arc700.c	ARC: cacheflush optim - PTAG can be loop invariant if V-P is const	2013-11-06 10:41:38 +05:30
dma.c	ARC: I/O and DMA Mappings	2013-02-15 23:15:54 +05:30
extable.c	ARC: Fix coding style issues	2013-04-09 12:21:14 +05:30
fault.c	ARC: Incorrect mm reference used in vmalloc fault handler	2013-11-02 10:27:04 -07:00
init.c	of: Specify initrd location using 64-bit	2013-07-24 11:10:01 +01:00
ioremap.c	ARC: Use <linux/*> headers instead of <asm/*>	2013-04-09 12:21:14 +05:30
Makefile	ARC: [mm] Aliasing VIPT dcache support 4/4	2013-05-09 22:00:57 +05:30
mmap.c	ARC: [mm] Aliasing VIPT dcache support 4/4	2013-05-09 22:00:57 +05:30
tlb.c	ARC: [ASID] Track ASID allocation cycles/generations	2013-08-30 21:42:19 +05:30
tlbex.S	ARC: [ASID] Track ASID allocation cycles/generations	2013-08-30 21:42:19 +05:30