32280d66fd
The DSI host and PHY driver currently expects the DT bindings to provide custom properties "qcom,dsi-host-index" and "qcom,dsi-phy-index" so that the driver can identify which DSI instance it is. The binding isn't acceptable, but the driver still needs to figure out what its instance id. This is now done by storing the mmio starting addresses for each DSI instance in every SoC version in the driver. The driver then identifies the index number by trying to match the stored address with comparing the resource start address we get from DT. We don't have compatible strings for DSI PHY on each SoC, but only the DSI PHY type. We only support one SoC version for each PHY type, so we get away doing the same thing above for the PHY driver. We can revisit this when we support two SoCs with the same DSI PHY. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DSI_PHY_H__
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#define __DSI_PHY_H__
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#include <linux/regulator/consumer.h>
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#include "dsi.h"
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#define dsi_phy_read(offset) msm_readl((offset))
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#define dsi_phy_write(offset, data) msm_writel((data), (offset))
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struct msm_dsi_phy_ops {
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int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
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const unsigned long bit_rate, const unsigned long esc_rate);
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void (*disable)(struct msm_dsi_phy *phy);
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};
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struct msm_dsi_phy_cfg {
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enum msm_dsi_phy_type type;
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struct dsi_reg_config reg_cfg;
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struct msm_dsi_phy_ops ops;
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/*
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* Each cell {phy_id, pll_id} of the truth table indicates
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* if the source PLL selection bit should be set for each PHY.
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* Fill default H/W values in illegal cells, eg. cell {0, 1}.
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*/
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bool src_pll_truthtable[DSI_MAX][DSI_MAX];
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const resource_size_t io_start[DSI_MAX];
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const int num_dsi_phy;
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};
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_pre;
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u32 clk_post;
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u32 clk_zero;
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u32 clk_trail;
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u32 clk_prepare;
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u32 hs_exit;
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u32 hs_zero;
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u32 hs_prepare;
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u32 hs_trail;
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u32 hs_rqst;
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u32 ta_go;
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u32 ta_sure;
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u32 ta_get;
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};
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struct msm_dsi_phy {
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struct platform_device *pdev;
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void __iomem *base;
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void __iomem *reg_base;
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int id;
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struct clk *ahb_clk;
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struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
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struct msm_dsi_dphy_timing timing;
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const struct msm_dsi_phy_cfg *cfg;
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bool regulator_ldo_mode;
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struct msm_dsi_pll *pll;
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};
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/*
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* PHY internal functions
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*/
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int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
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const unsigned long bit_rate, const unsigned long esc_rate);
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void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
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u32 bit_mask);
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#endif /* __DSI_PHY_H__ */
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