46ffadc7e6
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the MPLL clocks aren't changed (as these are reserved for audio). The only exception to this is the GXL S805X package because the 744MHz OPP isn't working correctly there. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com
18 lines
404 B
Plaintext
18 lines
404 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2017 BayLibre SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include "meson-gx-mali450.dtsi"
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&mali {
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compatible = "amlogic,meson-gxl-mali", "arm,mali-450";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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assigned-clocks = <&clkc CLKID_GP0_PLL>;
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assigned-clock-rates = <744000000>;
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};
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