d578759ed8
This branch contains various miscellaneous changes to code in the mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict with anything else. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSr3IGAAoJEMzrak5tbycxVVUP/09VfeFYOidIm6mgbWSMlL4l DEPzrGBOvyO60og4LIbDIgwDzkcEsxIF9erlrVTz1Fvh2p0P0sQycIKjvyhvNXeh Ft9TQ1kDHjoJcfHI9f8tapkmwhOG+6vy2gDrTPmyxjnLpiE5ccM18CCr5CMK+y2v Ojzmf2paPBFyI84gcdWuwF4Ze2YmwdHmG7TksG/PZrpicizSxe+d9wNVDBMkJnP6 QFicMU6DEFZVwwDkFx4qPYrFDJPk8dqcAmNl+F+9jGEqTmxA+7M8eOF/SQa62lwa OJrVugD8YigT5NjRW/9btOVY/jUHbg0Ekj5DXd7Q9rO5KNUrFDRSia5XiWmms/S8 QNJezmjNgA83OQDefuAkpsKydf1XGoyIQ9EjDUb4i807PRwTO4En+1pD0EpEWSet 0c1mfDvU5uC6L9A5VvR0pzyGz2U2EhNhkUz03WAqtWYdrR68vIZHNZVIvHOLuwWF fDkS26KxziOmKM1ePdL7wemuNOod8ACeyzXMa2dhR68l6LH1X1pnMaoxvk2AjETk SMat9tsxY827+TtQlAQ+4bdR3qXqYsQLD7VWOPO0V3fs5T08jVZrpJ9pHDRYW88K dGHmIW4sHXKXP4Qw9rDGWSkWZeOVJYr72U6uH9vbg8hK6Wi2eAMxZ27ngFiqahSK PIhnAfsdM2/FX+C+vu58 =Oztt -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc From Stephen Warren: ARM: tegra: SoC-specific core code changes This branch contains various miscellaneous changes to code in the mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict with anything else. * tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC ARM: tegra: use section-sized static mappings for LPAE too ARM: tegra: don't hard-code DEBUG_LL baud rate ARM: tegra: fix DEBUG_LL combined with LPAE ARM: tegra: switch FUSE clock on before usage Signed-off-by: Olof Johansson <olof@lixom.net>
85 lines
2.3 KiB
Plaintext
85 lines
2.3 KiB
Plaintext
config ARCH_TEGRA
|
|
bool "NVIDIA Tegra" if ARCH_MULTI_V7
|
|
select ARCH_HAS_CPUFREQ
|
|
select ARCH_REQUIRE_GPIOLIB
|
|
select ARM_GIC
|
|
select CLKSRC_MMIO
|
|
select CLKSRC_OF
|
|
select COMMON_CLK
|
|
select CPU_V7
|
|
select GENERIC_CLOCKEVENTS
|
|
select HAVE_ARM_SCU if SMP
|
|
select HAVE_ARM_TWD if SMP
|
|
select HAVE_SMP
|
|
select MIGHT_HAVE_CACHE_L2X0
|
|
select MIGHT_HAVE_PCI
|
|
select PINCTRL
|
|
select ARCH_HAS_RESET_CONTROLLER
|
|
select RESET_CONTROLLER
|
|
select SOC_BUS
|
|
select SPARSE_IRQ
|
|
select USB_ARCH_HAS_EHCI if USB_SUPPORT
|
|
select USB_ULPI if USB_PHY
|
|
select USB_ULPI_VIEWPORT if USB_PHY
|
|
select USE_OF
|
|
help
|
|
This enables support for NVIDIA Tegra based systems.
|
|
|
|
menu "NVIDIA Tegra options"
|
|
depends on ARCH_TEGRA
|
|
|
|
config ARCH_TEGRA_2x_SOC
|
|
bool "Enable support for Tegra20 family"
|
|
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
|
|
select ARM_ERRATA_720789
|
|
select ARM_ERRATA_754327 if SMP
|
|
select ARM_ERRATA_764369 if SMP
|
|
select PINCTRL_TEGRA20
|
|
select PL310_ERRATA_727915 if CACHE_L2X0
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
|
help
|
|
Support for NVIDIA Tegra AP20 and T20 processors, based on the
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
config ARCH_TEGRA_3x_SOC
|
|
bool "Enable support for Tegra30 family"
|
|
select ARM_ERRATA_754322
|
|
select ARM_ERRATA_764369 if SMP
|
|
select PINCTRL_TEGRA30
|
|
select PL310_ERRATA_769419 if CACHE_L2X0
|
|
help
|
|
Support for NVIDIA Tegra T30 processor family, based on the
|
|
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|
|
|
|
config ARCH_TEGRA_114_SOC
|
|
bool "Enable support for Tegra114 family"
|
|
select ARM_ERRATA_798181 if SMP
|
|
select ARM_L1_CACHE_SHIFT_6
|
|
select HAVE_ARM_ARCH_TIMER
|
|
select PINCTRL_TEGRA114
|
|
help
|
|
Support for NVIDIA Tegra T114 processor family, based on the
|
|
ARM CortexA15MP CPU
|
|
|
|
config ARCH_TEGRA_124_SOC
|
|
bool "Enable support for Tegra124 family"
|
|
select ARM_L1_CACHE_SHIFT_6
|
|
select HAVE_ARM_ARCH_TIMER
|
|
select PINCTRL_TEGRA124
|
|
help
|
|
Support for NVIDIA Tegra T124 processor family, based on the
|
|
ARM CortexA15MP CPU
|
|
|
|
config TEGRA_AHB
|
|
bool "Enable AHB driver for NVIDIA Tegra SoCs"
|
|
default y
|
|
help
|
|
Adds AHB configuration functionality for NVIDIA Tegra SoCs,
|
|
which controls AHB bus master arbitration and some
|
|
performance parameters(priority, prefech size).
|
|
|
|
config TEGRA_EMC_SCALING_ENABLE
|
|
bool "Enable scaling the memory frequency"
|
|
|
|
endmenu
|