d5f901eab2
The same reg table and read/write/rmw function are used by drivers based on qca8k family switch. Move them to common code to make it accessible also by other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
102 lines
3.1 KiB
C
102 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
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* Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016 John Crispin <john@phrozen.org>
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*/
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#include <linux/netdevice.h>
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#include <net/dsa.h>
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#include "qca8k.h"
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#define MIB_DESC(_s, _o, _n) \
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{ \
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.size = (_s), \
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.offset = (_o), \
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.name = (_n), \
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}
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const struct qca8k_mib_desc ar8327_mib[] = {
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MIB_DESC(1, 0x00, "RxBroad"),
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MIB_DESC(1, 0x04, "RxPause"),
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MIB_DESC(1, 0x08, "RxMulti"),
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MIB_DESC(1, 0x0c, "RxFcsErr"),
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MIB_DESC(1, 0x10, "RxAlignErr"),
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MIB_DESC(1, 0x14, "RxRunt"),
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MIB_DESC(1, 0x18, "RxFragment"),
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MIB_DESC(1, 0x1c, "Rx64Byte"),
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MIB_DESC(1, 0x20, "Rx128Byte"),
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MIB_DESC(1, 0x24, "Rx256Byte"),
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MIB_DESC(1, 0x28, "Rx512Byte"),
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MIB_DESC(1, 0x2c, "Rx1024Byte"),
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MIB_DESC(1, 0x30, "Rx1518Byte"),
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MIB_DESC(1, 0x34, "RxMaxByte"),
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MIB_DESC(1, 0x38, "RxTooLong"),
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MIB_DESC(2, 0x3c, "RxGoodByte"),
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MIB_DESC(2, 0x44, "RxBadByte"),
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MIB_DESC(1, 0x4c, "RxOverFlow"),
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MIB_DESC(1, 0x50, "Filtered"),
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MIB_DESC(1, 0x54, "TxBroad"),
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MIB_DESC(1, 0x58, "TxPause"),
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MIB_DESC(1, 0x5c, "TxMulti"),
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MIB_DESC(1, 0x60, "TxUnderRun"),
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MIB_DESC(1, 0x64, "Tx64Byte"),
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MIB_DESC(1, 0x68, "Tx128Byte"),
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MIB_DESC(1, 0x6c, "Tx256Byte"),
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MIB_DESC(1, 0x70, "Tx512Byte"),
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MIB_DESC(1, 0x74, "Tx1024Byte"),
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MIB_DESC(1, 0x78, "Tx1518Byte"),
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MIB_DESC(1, 0x7c, "TxMaxByte"),
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MIB_DESC(1, 0x80, "TxOverSize"),
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MIB_DESC(2, 0x84, "TxByte"),
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MIB_DESC(1, 0x8c, "TxCollision"),
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MIB_DESC(1, 0x90, "TxAbortCol"),
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MIB_DESC(1, 0x94, "TxMultiCol"),
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MIB_DESC(1, 0x98, "TxSingleCol"),
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MIB_DESC(1, 0x9c, "TxExcDefer"),
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MIB_DESC(1, 0xa0, "TxDefer"),
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MIB_DESC(1, 0xa4, "TxLateCol"),
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MIB_DESC(1, 0xa8, "RXUnicast"),
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MIB_DESC(1, 0xac, "TXUnicast"),
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};
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int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
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{
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return regmap_read(priv->regmap, reg, val);
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}
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int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
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{
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return regmap_write(priv->regmap, reg, val);
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}
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int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
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{
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return regmap_update_bits(priv->regmap, reg, mask, write_val);
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}
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static const struct regmap_range qca8k_readable_ranges[] = {
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regmap_reg_range(0x0000, 0x00e4), /* Global control */
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regmap_reg_range(0x0100, 0x0168), /* EEE control */
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regmap_reg_range(0x0200, 0x0270), /* Parser control */
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regmap_reg_range(0x0400, 0x0454), /* ACL */
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regmap_reg_range(0x0600, 0x0718), /* Lookup */
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regmap_reg_range(0x0800, 0x0b70), /* QM */
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regmap_reg_range(0x0c00, 0x0c80), /* PKT */
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regmap_reg_range(0x0e00, 0x0e98), /* L3 */
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regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
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regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
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regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
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regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
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regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
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regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
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regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
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};
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const struct regmap_access_table qca8k_readable_table = {
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.yes_ranges = qca8k_readable_ranges,
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.n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
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};
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