d62db60659
The address of the IVUR register is not correct, it should be offset into the MBAR region. Without this the vector is not set to the correct number. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/5249/config.c
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*
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* Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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/***************************************************************************/
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void coldfire_reset(void);
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/***************************************************************************/
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static struct mcf_platform_uart m5249_uart_platform[] = {
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{
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.mapbase = MCF_MBAR + MCFUART_BASE1,
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.irq = 73,
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},
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{
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.mapbase = MCF_MBAR + MCFUART_BASE2,
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.irq = 74,
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},
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{ },
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};
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static struct platform_device m5249_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m5249_uart_platform,
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};
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static struct platform_device *m5249_devices[] __initdata = {
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&m5249_uart,
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};
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/***************************************************************************/
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static void __init m5249_uart_init_line(int line, int irq)
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{
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if (line == 0) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
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mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1);
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} else if (line == 1) {
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writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
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writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
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mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2);
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}
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}
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static void __init m5249_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m5249_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m5249_uart_init_line(line, m5249_uart_platform[line].irq);
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}
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/***************************************************************************/
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void mcf_autovector(unsigned int vec)
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{
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volatile unsigned char *mbar;
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if ((vec >= 25) && (vec <= 31)) {
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mbar = (volatile unsigned char *) MCF_MBAR;
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vec = 0x1 << (vec - 24);
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*(mbar + MCFSIM_AVR) |= vec;
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mcf_setimr(mcf_getimr() & ~vec);
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}
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}
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/***************************************************************************/
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void mcf_settimericr(unsigned int timer, unsigned int level)
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{
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volatile unsigned char *icrp;
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unsigned int icr, imr;
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if (timer <= 2) {
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switch (timer) {
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case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
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default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
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}
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icrp = (volatile unsigned char *) (MCF_MBAR + icr);
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*icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
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mcf_setimr(mcf_getimr() & ~imr);
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}
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mcf_setimr(MCFSIM_IMR_MASKALL);
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mach_reset = coldfire_reset;
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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m5249_uarts_init();
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platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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