e62fc18213
Just as unevaluatedProperties or additionalProperties are required at the top level of schemas, they should (and will) also be required for child node schemas. That ensures only documented properties are present. Add unevaluatedProperties or additionalProperties as appropriate, and then add any missing properties flagged by the addition. Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230124230228.372305-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
108 lines
3.3 KiB
YAML
108 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel IXP4xx Expansion Bus Controller
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description: |
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The IXP4xx expansion bus controller handles access to devices on the
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memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
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including IXP42x, IXP43x, IXP45x and IXP46x.
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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properties:
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$nodename:
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pattern: '^bus@[0-9a-f]+$'
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compatible:
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items:
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- enum:
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- intel,ixp42x-expansion-bus-controller
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- intel,ixp43x-expansion-bus-controller
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- intel,ixp45x-expansion-bus-controller
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- intel,ixp46x-expansion-bus-controller
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- const: syscon
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reg:
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description: Control registers for the expansion bus, these are not
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inside the memory range handled by the expansion bus.
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maxItems: 1
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native-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: The IXP4xx has a peculiar MMIO access scheme, as it changes
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the access pattern for words (swizzling) on the bus depending on whether
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the SoC is running in big-endian or little-endian mode. Thus the
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registers must always be accessed using native endianness.
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"#address-cells":
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description: |
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The first cell is the chip select number.
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The second cell is the address offset within the bank.
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const: 2
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"#size-cells":
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const: 1
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ranges: true
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dma-ranges: true
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patternProperties:
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"^.*@[0-7],[0-9a-f]+$":
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description: Devices attached to chip selects are represented as
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subnodes.
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type: object
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$ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
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additionalProperties: true
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required:
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- compatible
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- reg
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- native-endian
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- "#address-cells"
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- "#size-cells"
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- ranges
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- dma-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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bus@50000000 {
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compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
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reg = <0xc4000000 0x28>;
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native-endian;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x50000000 0x01000000>,
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<1 0x0 0x51000000 0x01000000>;
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dma-ranges = <0 0x0 0x50000000 0x01000000>,
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<1 0x0 0x51000000 0x01000000>;
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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reg = <0 0x00000000 0x1000000>;
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-cycle-type = <0>;
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intel,ixp4xx-eb-byte-access-on-halfword = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <0>;
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};
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serial@1,0 {
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compatible = "exar,xr16l2551", "ns8250";
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reg = <1 0x00000000 0x10>;
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interrupt-parent = <&gpio0>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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clock-frequency = <1843200>;
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intel,ixp4xx-eb-t3 = <3>;
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intel,ixp4xx-eb-cycle-type = <1>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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};
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};
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