dc8ea9204b
There's a bunch of bindings for (mostly l2) cache controllers scattered to the four winds, move them to a common directory. I renamed the freescale l2cache.txt file, as while that might make sense when the parent dir is fsl, it's confusing after the move. The two Marvell bindings have had a "marvell," prefix added to match their compatibles. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> |
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| .. | ||
| 4xx | ||
| fsl | ||
| nintendo | ||
| opal | ||
| ibm,powerpc-cpu-features.txt | ||
| ibm,vas.txt | ||
| sleep.yaml | ||