12a18bb74f
Almost all Qualcomm SoC Top Level Mode Multiplexers come with only summary interrupt. SM6350 is different because downstream and upstream DTS have nine of the interrupts. Allow such variation. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221230135645.56401-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
153 lines
4.1 KiB
YAML
153 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
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maintainers:
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- Iskren Chernev <iskren.chernev@gmail.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115
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SoCs.
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properties:
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compatible:
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const: qcom,sm6115-tlmm
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: south
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- const: east
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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gpio-reserved-ranges: true
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wakeup-parent: true
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm6115-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm6115-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm6115-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
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sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
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cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
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gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
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mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
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m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
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pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
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qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
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sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
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uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
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uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
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wlan1_adc0, elan1_adc1 ]
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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drive-strength: true
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output-high: true
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output-low: true
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required:
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- pins
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additionalProperties: false
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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- reg-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@500000 {
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compatible = "qcom,sm6115-tlmm";
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reg = <0x500000 0x400000>,
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<0x900000 0x400000>,
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<0xd00000 0x400000>;
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reg-names = "west", "south", "east";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 114>;
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sdc2_on_state: sdc2-on-state {
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clk-pins {
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pins = "sdc2_clk";
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bias-disable;
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drive-strength = <16>;
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};
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cmd-pins {
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pins = "sdc2_cmd";
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bias-pull-up;
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drive-strength = <10>;
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};
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data-pins {
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pins = "sdc2_data";
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bias-pull-up;
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drive-strength = <10>;
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};
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sd-cd-pins {
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pins = "gpio88";
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function = "gpio";
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bias-pull-up;
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drive-strength = <2>;
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};
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};
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};
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