979bb59016
New drivers:
- Cypress CY8C95x0 chip pin control support, along with an immediate
cleanup.
- Mediatek MT8188 SoC pin control support.
- Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem)
pin control support.
- Qualcomm PM7250, PM8450
- Rockchip RV1126 SoC pin control support.
Improvements:
- Fix some missing pins in the Armada 37xx driver.
- Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP() macro.
- Fix some GPIO irq_chips to be immutable.
- Massive Qualcomm device tree binding cleanup, with more to come.
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Merge tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"There is nothing exciting going on, no core changes, just a few
drivers and cleanups.
New drivers:
- Cypress CY8C95x0 chip pin control support, along with an immediate
cleanup
- Mediatek MT8188 SoC pin control support
- Qualcomm SM8450 and SC8280XP LPASS (low power audio subsystem) pin
control support
- Qualcomm PM7250, PM8450
- Rockchip RV1126 SoC pin control support
Improvements:
- Fix some missing pins in the Armada 37xx driver
- Convert Broadcom and Nomadik drivers to use PINCTRL_PINGROUP()
macro
- Fix some GPIO irq_chips to be immutable
- Massive Qualcomm device tree binding cleanup, with more to come"
* tag 'pinctrl-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (119 commits)
MAINTAINERS: adjust STARFIVE JH7100 PINCTRL DRIVER after file movement
pinctrl: starfive: Rename "pinctrl-starfive" to "pinctrl-starfive-jh7100"
pinctrl: Create subdirectory for StarFive drivers
dt-bindings: pinctrl: st,stm32: Document interrupt-controller property
dt-bindings: pinctrl: st,stm32: Document gpio-hog pattern property
dt-bindings: pinctrl: st,stm32: Document gpio-line-names
pinctrl: st: stop abusing of_get_named_gpio()
pinctrl: wpcm450: Correct the fwnode_irq_get() return value check
pinctrl: bcm: Remove unused struct bcm6328_pingroup
pinctrl: qcom: restrict drivers per ARM/ARM64
pinctrl: bcm: ns: Remove redundant dev_err call
gpio: rockchip: request GPIO mux to pinctrl when setting direction
pinctrl: rockchip: add pinmux_ops.gpio_set_direction callback
pinctrl: cy8c95x0: Align function names in cy8c95x0_pmxops
pinctrl: cy8c95x0: Drop atomicity on operations on push_pull
pinctrl: cy8c95x0: Lock register accesses in cy8c95x0_set_mux()
pinctrl: sunxi: sun50i-h5: Switch to use dev_err_probe() helper
pinctrl: stm32: Switch to use dev_err_probe() helper
dt-bindings: qcom-pmic-gpio: Add PM7250B and PM8450 bindings
pinctrl: qcom: spmi-gpio: Add compatible for PM7250B
...
308 lines
9.7 KiB
YAML
308 lines
9.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7100 Pin Controller
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description: |
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Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
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Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
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and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
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configurable bias, drive strength, schmitt trigger etc. The SoC has an
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interesting 2-layered approach to pin muxing best illustrated by the diagram
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below.
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Signal group 0, 1, ... or 6
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___|___
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LCD output -----------------| |
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CMOS Camera interface ------| |--- PAD_GPIO[0]
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Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
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... | | ...
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| |--- PAD_GPIO[63]
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-------- GPIO0 ------------| |
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| -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0]
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| | | | | |--- PAD_FUNC_SHARE[1]
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| | | | ... | | ...
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| | | | | |--- PAD_FUNC_SHARE[141]
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| | -----|---|-- GPIO63 ---| |
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| | | | | | -------
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UART0 UART1 --
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The big MUX in the diagram only has 7 different ways of mapping peripherals
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on the left to pins on the right. StarFive calls the 7 configurations "signal
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groups".
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However some peripherals have their I/O go through the 64 "GPIOs". The
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diagram only shows UART0 and UART1, but this also includes a number of other
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UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
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GPIOs such that any GPIO can be set up to be controlled by any of the
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peripherals.
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Note that signal group 0 doesn't map any of the GPIOs to pins, and only
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signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
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maintainers:
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- Emil Renner Berthing <kernel@esmil.dk>
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- Drew Fustini <drew@beagleboard.org>
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properties:
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compatible:
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const: starfive,jh7100-pinctrl
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reg:
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minItems: 2
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maxItems: 2
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reg-names:
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items:
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- const: gpio
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- const: padctl
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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gpio-controller: true
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"#gpio-cells":
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const: 2
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interrupts:
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maxItems: 1
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description: The GPIO parent interrupt.
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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starfive,signal-group:
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description: |
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Select one of the 7 signal groups. If this property is not set it
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defaults to the configuration already chosen by the earlier boot stages.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3, 4, 5, 6]
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- gpio-controller
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- "#gpio-cells"
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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patternProperties:
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'-[0-9]+$':
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type: object
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patternProperties:
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'-pins$':
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type: object
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description: |
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A pinctrl node should contain at least one subnode representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to
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muxer configuration, bias, input enable/disable, input schmitt
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trigger enable/disable, slew-rate and drive strength.
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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properties:
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pins:
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description: |
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The list of pin identifiers that properties in the node apply to.
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This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
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macros.
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Either this or "pinmux" has to be specified, but not both.
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$ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
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pinmux:
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description: |
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The list of GPIOs and their mux settings that properties in the
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node apply to. This should be set using the GPIOMUX macro.
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Either this or "pins" has to be specified, but not both.
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$ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
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bias-disable: true
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bias-pull-up:
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type: boolean
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bias-pull-down:
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type: boolean
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drive-strength:
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enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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slew-rate:
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maximum: 7
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starfive,strong-pull-up:
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description: enable strong pull-up.
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type: boolean
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additionalProperties: false
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additionalProperties: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive-jh7100.h>
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#include <dt-bindings/reset/starfive-jh7100.h>
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#include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pinctrl@11910000 {
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compatible = "starfive,jh7100-pinctrl";
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reg = <0x0 0x11910000 0x0 0x10000>,
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<0x0 0x11858000 0x0 0x1000>;
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reg-names = "gpio", "padctl";
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clocks = <&clkgen JH7100_CLK_GPIO_APB>;
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resets = <&clkgen JH7100_RSTN_GPIO_APB>;
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interrupts = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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starfive,signal-group = <6>;
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gmac_pins_default: gmac-0 {
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gtxclk-pins {
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pins = <PAD_FUNC_SHARE(115)>;
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bias-pull-up;
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drive-strength = <35>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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miitxclk-pins {
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pins = <PAD_FUNC_SHARE(116)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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tx-pins {
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pins = <PAD_FUNC_SHARE(117)>,
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<PAD_FUNC_SHARE(119)>,
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<PAD_FUNC_SHARE(120)>,
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<PAD_FUNC_SHARE(121)>,
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<PAD_FUNC_SHARE(122)>,
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<PAD_FUNC_SHARE(123)>,
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<PAD_FUNC_SHARE(124)>,
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<PAD_FUNC_SHARE(125)>,
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<PAD_FUNC_SHARE(126)>;
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bias-disable;
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drive-strength = <35>;
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input-disable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rxclk-pins {
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pins = <PAD_FUNC_SHARE(127)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <6>;
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};
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rxer-pins {
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pins = <PAD_FUNC_SHARE(129)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-disable;
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slew-rate = <0>;
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};
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rx-pins {
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pins = <PAD_FUNC_SHARE(128)>,
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<PAD_FUNC_SHARE(130)>,
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<PAD_FUNC_SHARE(131)>,
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<PAD_FUNC_SHARE(132)>,
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<PAD_FUNC_SHARE(133)>,
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<PAD_FUNC_SHARE(134)>,
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<PAD_FUNC_SHARE(135)>,
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<PAD_FUNC_SHARE(136)>,
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<PAD_FUNC_SHARE(137)>,
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<PAD_FUNC_SHARE(138)>,
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<PAD_FUNC_SHARE(139)>,
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<PAD_FUNC_SHARE(140)>,
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<PAD_FUNC_SHARE(141)>;
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bias-pull-up;
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drive-strength = <14>;
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input-enable;
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input-schmitt-enable;
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slew-rate = <0>;
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};
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};
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i2c0_pins_default: i2c0-0 {
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i2c-pins {
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pinmux = <GPIOMUX(62, GPO_LOW,
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GPO_I2C0_PAD_SCK_OEN,
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GPI_I2C0_PAD_SCK_IN)>,
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<GPIOMUX(61, GPO_LOW,
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GPO_I2C0_PAD_SDA_OEN,
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GPI_I2C0_PAD_SDA_IN)>;
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bias-disable; /* external pull-up */
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input-enable;
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input-schmitt-enable;
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};
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};
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uart3_pins_default: uart3-0 {
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rx-pins {
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pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
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GPI_UART3_PAD_SIN)>;
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bias-pull-up;
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input-enable;
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input-schmitt-enable;
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};
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tx-pins {
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pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
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GPO_ENABLE, GPI_NONE)>;
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bias-disable;
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input-disable;
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input-schmitt-disable;
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};
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};
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};
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gmac {
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pinctrl-0 = <&gmac_pins_default>;
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pinctrl-names = "default";
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};
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i2c0 {
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pinctrl-0 = <&i2c0_pins_default>;
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pinctrl-names = "default";
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};
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uart3 {
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pinctrl-0 = <&uart3_pins_default>;
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pinctrl-names = "default";
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};
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};
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...
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