d76271d226
The Xilinx ZynqMP SoC has a hardened display pipeline named DisplayPort Subsystem. It includes a buffer manager, a video pipeline renderer (blender), an audio mixer and a DisplayPort source controller (transmitter). The DMA engine the provide data to the buffer manager, as well as the DisplayPort PHYs that drive the lanes, are external to the subsystem and interfaced using the DMA engine and PHY APIs respectively. This driver supports the DisplayPort Subsystem and implements - Two planes, for graphics and video - One CRTC that supports alpha blending - One encoder for the DisplayPort transmitter - One connector for an external monitor It currently doesn't support - Color keying - Test pattern generation - Audio - Live input from the Programmable Logic (FPGA) - Output to the Programmable Logic (FPGA) Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.