Linus Torvalds 58d4fafd0b RISC-V updates for v5.4-rc1 ...

Add the following new features:
 
 - Generic CPU topology description support for DT-based platforms,
   including ARM64, ARM and RISC-V.
 
 - Sparsemem support
 
 - Perf callchain support
 
 - SiFive PLIC irqchip modifications, in preparation for M-mode Linux
 
 and clean up the code base:
 
 - Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
   flushing, and the RISC-V CPU-local timer code
 
 - Kbuild cleanup from one of the Kbuild maintainers
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Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Paul Walmsley:
 "Add the following new features:

   - Generic CPU topology description support for DT-based platforms,
     including ARM64, ARM and RISC-V.

   - Sparsemem support

   - Perf callchain support

   - SiFive PLIC irqchip modifications, in preparation for M-mode Linux

  and clean up the code base:

   - Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
     flushing, and the RISC-V CPU-local timer code

   - Kbuild cleanup from one of the Kbuild maintainers"

[ The CPU topology parts came in through the arm64 tree with a shared
  branch   - Linus ]

* tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  irqchip/sifive-plic: set max threshold for ignored handlers
  riscv: move the TLB flush logic out of line
  riscv: don't use the rdtime(h) pseudo-instructions
  riscv: cleanup riscv_cpuid_to_hartid_mask
  riscv: optimize send_ipi_single
  riscv: cleanup send_ipi_mask
  riscv: refactor the IPI code
  riscv: Add support for libdw
  riscv: Add support for perf registers sampling
  riscv: Add perf callchain support
  riscv: add arch/riscv/Kbuild
  RISC-V: Implement sparsemem
  riscv: Using CSR numbers to access CSRs

2019-09-16 15:29:34 -07:00

..

asm

RISC-V updates for v5.4-rc1

2019-09-16 15:29:34 -07:00

uapi/asm

riscv: Add support for perf registers sampling

2019-09-05 00:48:58 -07:00