Remi Pommarel d8488a4180 clk: meson: pll: Fix by 0 division in __pll_params_to_rate() ... Some meson pll registers can be initialized with 0 as N value, introducing the following division by 0 when computing rate : UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9 division by zero CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400 Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x14/0x20 dump_stack+0xc4/0x100 ubsan_epilogue+0x14/0x68 __ubsan_handle_divrem_overflow+0x98/0xb8 __pll_params_to_rate+0xdc/0x140 meson_clk_pll_recalc_rate+0x278/0x3a0 __clk_register+0x7c8/0xbb0 devm_clk_hw_register+0x54/0xc0 meson_eeclkc_probe+0xf4/0x1a0 platform_drv_probe+0x54/0xd8 really_probe+0x16c/0x438 driver_probe_device+0xb0/0xf0 device_driver_attach+0x94/0xa0 __driver_attach+0x70/0x108 bus_for_each_dev+0xd8/0x128 driver_attach+0x30/0x40 bus_add_driver+0x1b0/0x2d8 driver_register+0xbc/0x1d0 __platform_driver_register+0x78/0x88 axg_driver_init+0x18/0x20 do_one_initcall+0xc8/0x24c kernel_init_freeable+0x2b0/0x344 kernel_init+0x10/0x128 ret_from_fork+0x10/0x18 This checks if N is null before doing the division. Fixes: 7a29a86943 ("clk: meson: Add support for Meson clock controller") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt> [jbrunet@baylibre.com: update the comment in above the fix] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>		2019-12-16 10:58:57 +01:00
..
axg-aoclk.c	clk: meson: axg-aoclk: migrate to the new parent description method	2019-07-29 12:42:48 +02:00
axg-aoclk.h	clk: meson: axg-ao: add 32k generation subtree	2019-01-07 15:21:43 +01:00
axg-audio.c	clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code	2019-10-14 17:06:27 +02:00
axg-audio.h	clk: meson: axg_audio: add sm1 support	2019-10-08 09:29:23 +02:00
axg.c	clk: meson: clk-regmap: migrate to new parent description method	2019-07-29 12:42:49 +02:00
axg.h	clk: meson: clk-pll: remove od parameters	2018-09-26 12:01:57 +02:00
clk-cpu-dyndiv.c	clk: meson: add g12a cpu dynamic divider driver	2019-08-09 12:10:03 +02:00
clk-cpu-dyndiv.h	clk: meson: add g12a cpu dynamic divider driver	2019-08-09 12:10:03 +02:00
clk-dualdiv.c	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
clk-dualdiv.h	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
clk-mpll.c	clk: meson: mpll: add init callback and regs	2019-05-20 12:19:29 +02:00
clk-mpll.h	clk: meson: mpll: add init callback and regs	2019-05-20 12:19:29 +02:00
clk-phase.c	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
clk-phase.h	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
clk-pll.c	clk: meson: pll: Fix by 0 division in __pll_params_to_rate()	2019-12-16 10:58:57 +01:00
clk-pll.h	clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL	2019-04-01 10:45:11 +02:00
clk-regmap.c	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
clk-regmap.h	clk: meson: clk-regmap: migrate to new parent description method	2019-07-29 12:42:49 +02:00
g12a-aoclk.c	clk: meson: g12a-aoclk: migrate to the new parent description method	2019-07-29 12:42:48 +02:00
g12a-aoclk.h	dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN	2019-04-01 10:45:11 +02:00
g12a.c	clk: meson: g12a: fix missing uart2 in regmap table	2019-12-16 10:28:38 +01:00
g12a.h	clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks	2019-08-26 11:04:54 +02:00
gxbb-aoclk.c	clk: meson: gxbb-aoclk: migrate to the new parent description method	2019-07-29 12:42:48 +02:00
gxbb-aoclk.h	clk: meson: gxbb-ao: replace cec-32k with the dual divider	2019-01-07 15:21:22 +01:00
gxbb.c	clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate	2019-10-01 14:46:30 +02:00
gxbb.h	dt-bindings: clk: meson-gxbb: Add Video clock bindings	2018-11-23 15:11:56 +01:00
Kconfig	clk: meson: add g12a cpu dynamic divider driver	2019-08-09 12:10:03 +02:00
Makefile	clk: meson: add g12a cpu dynamic divider driver	2019-08-09 12:10:03 +02:00
meson8b.c	clk: meson: clk-regmap: migrate to new parent description method	2019-07-29 12:42:49 +02:00
meson8b.h	clk: meson: meson8b: add the cts_i958 clock	2019-06-11 11:02:04 +02:00
meson-aoclk.c	clk: meson: remove ao input bypass clocks	2019-07-29 12:42:48 +02:00
meson-aoclk.h	clk: meson: remove ao input bypass clocks	2019-07-29 12:42:48 +02:00
meson-eeclk.c	clk: meson: remove ee input bypass clocks	2019-07-29 12:42:49 +02:00
meson-eeclk.h	clk: meson: remove ee input bypass clocks	2019-07-29 12:42:49 +02:00
parm.h	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
sclk-div.c	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
sclk-div.h	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00
vid-pll-div.c	clk: meson: vid-pll-div: remove warning and return 0 on invalid config	2019-03-29 09:41:30 +01:00
vid-pll-div.h	clk: meson: rework and clean drivers dependencies	2019-02-02 17:43:32 +01:00