d8989d96eb
When the MCLK is used to drive the Audio Clock Regeneration packets, the initialization procedure is to set ACR_CTRL[2] to 0 and then back again to 1. Also, devices that do not support the MCLK, use the TMDS clock directly by leaving ACR_CTRL[2] set to 0. The MLCK clock divisor, mclk_mode, is configured only if MLCK is used. Such configuration is no longer related to the CTS mode as in some silicon revisions CTS SW-mode is used along with the MCLK. Signed-off-by: Ricardo Neri <ricardo.neri@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> |
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| displays | ||
| dss | ||
| omapfb | ||
| Kconfig | ||
| Makefile | ||
| vram.c | ||
| vrfb.c | ||