d8f5840992
The DRAM refresh-interval is getting erroneously set to "1" on exiting from memory self-refreshing mode. The clobbered interval causes the "refresh request overflow timeout" error raised by the External Memory Controller on exiting from LP1 on Tegra30. The same may happen on Tegra20, but EMC registers are not latched after exiting from self-refreshing mode on Tegra20 and hence refresh-interval is not altered until an event that causes registers latching happens. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> |
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.. | ||
board-paz00.c | ||
board.h | ||
common.h | ||
cpuidle-tegra20.c | ||
cpuidle-tegra30.c | ||
cpuidle-tegra114.c | ||
cpuidle.c | ||
cpuidle.h | ||
hotplug.c | ||
io.c | ||
iomap.h | ||
irammap.h | ||
irq.c | ||
irq.h | ||
Kconfig | ||
Makefile | ||
platsmp.c | ||
pm-tegra20.c | ||
pm-tegra30.c | ||
pm.c | ||
pm.h | ||
reset-handler.S | ||
reset.c | ||
reset.h | ||
sleep-tegra20.S | ||
sleep-tegra30.S | ||
sleep.h | ||
sleep.S | ||
tegra.c |