d8f64797c5
Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
29 lines
863 B
Plaintext
29 lines
863 B
Plaintext
NVIDIA Tegra20 SFLASH controller.
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Required properties:
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- compatible : should be "nvidia,tegra20-sflash".
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- reg: Should contain SFLASH registers location and length.
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- interrupts: Should contain SFLASH interrupts.
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- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
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request selector for this SFLASH controller.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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Recommended properties:
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- spi-max-frequency: Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Example:
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spi@7000c380 {
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compatible = "nvidia,tegra20-sflash";
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reg = <0x7000c380 0x80>;
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interrupts = <0 39 0x04>;
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nvidia,dma-request-selector = <&apbdma 16>;
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spi-max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 43>;
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status = "disabled";
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};
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