d9a2012d32
Update MPU, IVA and CORE voltage Rail values obtained from OMAP4430 Data Manual Operating Condition Addendum_v0.4. Tested on OMAP4430 SDP Board. Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
99 lines
3.4 KiB
C
99 lines
3.4 KiB
C
/*
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* OMAP4 OPP table definitions.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* Nishanth Menon
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* Kevin Hilman
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* Thara Gopinath
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* Copyright (C) 2010-2011 Nokia Corporation.
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* Eduardo Valentin
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <plat/cpu.h>
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#include "control.h"
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#include "omap_opp_data.h"
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/*
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* Structures containing OMAP4430 voltage supported and various
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* voltage dependent data for each VDD.
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*/
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#define OMAP4430_VDD_MPU_OPP50_UV 1025000
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#define OMAP4430_VDD_MPU_OPP100_UV 1200000
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#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000
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#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000
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struct omap_volt_data omap44xx_vdd_mpu_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
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VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
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VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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#define OMAP4430_VDD_IVA_OPP50_UV 1013000
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#define OMAP4430_VDD_IVA_OPP100_UV 1188000
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#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000
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struct omap_volt_data omap44xx_vdd_iva_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
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VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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#define OMAP4430_VDD_CORE_OPP50_UV 1025000
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#define OMAP4430_VDD_CORE_OPP100_UV 1200000
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struct omap_volt_data omap44xx_vdd_core_volt_data[] = {
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VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),
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VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP100_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP100, 0xf9, 0x16),
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VOLT_DATA_DEFINE(0, 0, 0, 0),
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};
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static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
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/* MPU OPP1 - OPP50 */
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OPP_INITIALIZER("mpu", true, 300000000, OMAP4430_VDD_MPU_OPP50_UV),
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/* MPU OPP2 - OPP100 */
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OPP_INITIALIZER("mpu", true, 600000000, OMAP4430_VDD_MPU_OPP100_UV),
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/* MPU OPP3 - OPP-Turbo */
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OPP_INITIALIZER("mpu", true, 800000000, OMAP4430_VDD_MPU_OPPTURBO_UV),
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/* MPU OPP4 - OPP-SB */
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OPP_INITIALIZER("mpu", true, 1008000000, OMAP4430_VDD_MPU_OPPNITRO_UV),
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/* L3 OPP1 - OPP50 */
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OPP_INITIALIZER("l3_main_1", true, 100000000, OMAP4430_VDD_CORE_OPP50_UV),
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/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
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OPP_INITIALIZER("l3_main_1", true, 200000000, OMAP4430_VDD_CORE_OPP100_UV),
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/* TODO: add IVA, DSP, aess, fdif, gpu */
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};
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/**
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* omap4_opp_init() - initialize omap4 opp table
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*/
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static int __init omap4_opp_init(void)
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{
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int r = -ENODEV;
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if (!cpu_is_omap44xx())
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return r;
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r = omap_init_opp_table(omap44xx_opp_def_list,
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ARRAY_SIZE(omap44xx_opp_def_list));
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return r;
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}
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device_initcall(omap4_opp_init);
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