db67befa3d
T5/T6 can have different pack and pad boundary value. This patch sets packing boundary based on cache line size and PCI-E maximum payload size and sets smallest padding boundary value. Signed-off-by: Varun Prakash <varun@chelsio.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com> |
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.. | ||
csio_attr.c | ||
csio_defs.h | ||
csio_hw_chip.h | ||
csio_hw_t5.c | ||
csio_hw.c | ||
csio_hw.h | ||
csio_init.c | ||
csio_init.h | ||
csio_isr.c | ||
csio_lnode.c | ||
csio_lnode.h | ||
csio_mb.c | ||
csio_mb.h | ||
csio_rnode.c | ||
csio_rnode.h | ||
csio_scsi.c | ||
csio_scsi.h | ||
csio_wr.c | ||
csio_wr.h | ||
Kconfig | ||
Makefile | ||
t4fw_api_stor.h |