db8be50c43
We are seeing a number of crashes in SMM, when VT-d is enabled while
'Legacy USB support' is enabled in various BIOSes.
The BIOS is supposed to indicate which addresses it uses for DMA in a
special ACPI table ("RMRR"), so that we can punch a hole for it when we
set up the IOMMU.
The problem is, as usual, that BIOS engineers are totally incompetent.
They write code which will crash if the DMA goes AWOL, and then they
either neglect to provide an RMRR table at all, or they put the wrong
addresses in it. And of course they don't do _any_ QA, since that would
take too much time away from their crack-smoking habit.
The real fix, of course, is for consumers to refuse to buy motherboards
which only have closed-source firmware available. If we had _open_
firmware, bugs like this would be easy to fix.
Since that's something I can only dream about, this patch implements an
alternative -- ensuring that the USB controllers are handed off from the
BIOS and quiesced _before_ the IOMMU is initialised. That would have
been a much better design than this RMRR nonsense in the first place, of
course. The bootloader has no business doing DMA after the OS has booted
anyway.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
479 lines
14 KiB
C
479 lines
14 KiB
C
/*
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* This file contains code to reset and initialize USB host controllers.
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* Some of it includes work-arounds for PCI hardware and BIOS quirks.
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* It may need to run early during booting -- before USB would normally
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* initialize -- to ensure that Linux doesn't use any legacy modes.
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*
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* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
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* (and others)
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/acpi.h>
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#include "pci-quirks.h"
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#include "xhci-ext-caps.h"
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#define UHCI_USBLEGSUP 0xc0 /* legacy support */
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#define UHCI_USBCMD 0 /* command register */
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#define UHCI_USBINTR 4 /* interrupt register */
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#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
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#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
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#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
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#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
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#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
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#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
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#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
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#define OHCI_CONTROL 0x04
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#define OHCI_CMDSTATUS 0x08
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#define OHCI_INTRSTATUS 0x0c
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#define OHCI_INTRENABLE 0x10
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#define OHCI_INTRDISABLE 0x14
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#define OHCI_OCR (1 << 3) /* ownership change request */
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#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
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#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
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#define OHCI_INTR_OC (1 << 30) /* ownership change */
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#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
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#define EHCI_USBCMD 0 /* command register */
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#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
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#define EHCI_USBSTS 4 /* status register */
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#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
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#define EHCI_USBINTR 8 /* interrupt register */
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#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
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#define EHCI_USBLEGSUP 0 /* legacy support register */
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#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
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#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
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#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
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#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
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/*
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* Make sure the controller is completely inactive, unable to
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* generate interrupts or do DMA.
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*/
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void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
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{
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/* Turn off PIRQ enable and SMI enable. (This also turns off the
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* BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
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*/
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pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
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/* Reset the HC - this will force us to get a
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* new notification of any already connected
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* ports due to the virtual disconnect that it
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* implies.
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*/
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outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
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mb();
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udelay(5);
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if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
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dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
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/* Just to be safe, disable interrupt requests and
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* make sure the controller is stopped.
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*/
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outw(0, base + UHCI_USBINTR);
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outw(0, base + UHCI_USBCMD);
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}
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EXPORT_SYMBOL_GPL(uhci_reset_hc);
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/*
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* Initialize a controller that was newly discovered or has just been
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* resumed. In either case we can't be sure of its previous state.
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*
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* Returns: 1 if the controller was reset, 0 otherwise.
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*/
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int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
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{
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u16 legsup;
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unsigned int cmd, intr;
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/*
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* When restarting a suspended controller, we expect all the
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* settings to be the same as we left them:
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*
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* PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
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* Controller is stopped and configured with EGSM set;
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* No interrupts enabled except possibly Resume Detect.
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*
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* If any of these conditions are violated we do a complete reset.
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*/
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pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
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if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
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dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
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__func__, legsup);
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goto reset_needed;
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}
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cmd = inw(base + UHCI_USBCMD);
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if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
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!(cmd & UHCI_USBCMD_EGSM)) {
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dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
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__func__, cmd);
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goto reset_needed;
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}
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intr = inw(base + UHCI_USBINTR);
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if (intr & (~UHCI_USBINTR_RESUME)) {
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dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
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__func__, intr);
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goto reset_needed;
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}
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return 0;
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reset_needed:
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dev_dbg(&pdev->dev, "Performing full reset\n");
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uhci_reset_hc(pdev, base);
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return 1;
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}
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EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
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static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
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{
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u16 cmd;
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return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
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}
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#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
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#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
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static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
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{
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unsigned long base = 0;
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int i;
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if (!pio_enabled(pdev))
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return;
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for (i = 0; i < PCI_ROM_RESOURCE; i++)
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if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
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base = pci_resource_start(pdev, i);
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break;
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}
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if (base)
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uhci_check_and_reset_hc(pdev, base);
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}
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static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
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{
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return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
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}
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static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
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{
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void __iomem *base;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = pci_ioremap_bar(pdev, 0);
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if (base == NULL)
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return;
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/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
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#ifndef __hppa__
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{
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u32 control = readl(base + OHCI_CONTROL);
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if (control & OHCI_CTRL_IR) {
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int wait_time = 500; /* arbitrary; 5 seconds */
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writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
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writel(OHCI_OCR, base + OHCI_CMDSTATUS);
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while (wait_time > 0 &&
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readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
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wait_time -= 10;
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msleep(10);
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}
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if (wait_time <= 0)
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dev_warn(&pdev->dev, "OHCI: BIOS handoff failed"
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" (BIOS bug?) %08x\n",
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readl(base + OHCI_CONTROL));
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/* reset controller, preserving RWC */
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writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL);
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}
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}
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#endif
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/*
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* disable interrupts
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*/
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writel(~(u32)0, base + OHCI_INTRDISABLE);
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writel(~(u32)0, base + OHCI_INTRSTATUS);
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iounmap(base);
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}
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static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
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{
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int wait_time, delta;
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void __iomem *base, *op_reg_base;
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u32 hcc_params, val;
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u8 offset, cap_length;
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int count = 256/4;
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int tried_handoff = 0;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = pci_ioremap_bar(pdev, 0);
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if (base == NULL)
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return;
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cap_length = readb(base);
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op_reg_base = base + cap_length;
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/* EHCI 0.96 and later may have "extended capabilities"
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* spec section 5.1 explains the bios handoff, e.g. for
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* booting from USB disk or using a usb keyboard
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*/
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hcc_params = readl(base + EHCI_HCC_PARAMS);
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offset = (hcc_params >> 8) & 0xff;
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while (offset && --count) {
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u32 cap;
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int msec;
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pci_read_config_dword(pdev, offset, &cap);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff support */
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if ((cap & EHCI_USBLEGSUP_BIOS)) {
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dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
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#if 0
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/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
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* but that seems dubious in general (the BIOS left it off intentionally)
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* and is known to prevent some systems from booting. so we won't do this
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* unless maybe we can determine when we're on a system that needs SMI forced.
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*/
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/* BIOS workaround (?): be sure the
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* pre-Linux code receives the SMI
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*/
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pci_read_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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&val);
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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val | EHCI_USBLEGCTLSTS_SOOE);
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#endif
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/* some systems get upset if this semaphore is
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* set for any other reason than forcing a BIOS
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* handoff..
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*/
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pci_write_config_byte(pdev, offset + 3, 1);
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}
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/* if boot firmware now owns EHCI, spin till
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* it hands it over.
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*/
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msec = 1000;
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while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
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tried_handoff = 1;
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msleep(10);
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msec -= 10;
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pci_read_config_dword(pdev, offset, &cap);
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}
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if (cap & EHCI_USBLEGSUP_BIOS) {
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/* well, possibly buggy BIOS... try to shut
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* it down, and hope nothing goes too wrong
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*/
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dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
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" (BIOS bug?) %08x\n", cap);
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pci_write_config_byte(pdev, offset + 2, 0);
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}
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/* just in case, always disable EHCI SMIs */
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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0);
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/* If the BIOS ever owned the controller then we
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* can't expect any power sessions to remain intact.
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*/
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if (tried_handoff)
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writel(0, op_reg_base + EHCI_CONFIGFLAG);
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break;
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case 0: /* illegal reserved capability */
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cap = 0;
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/* FALLTHROUGH */
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default:
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dev_warn(&pdev->dev, "EHCI: unrecognized capability "
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"%02x\n", cap & 0xff);
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break;
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}
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offset = (cap >> 8) & 0xff;
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}
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if (!count)
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dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
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/*
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* halt EHCI & disable its interrupts in any case
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*/
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val & EHCI_USBSTS_HALTED) == 0) {
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val = readl(op_reg_base + EHCI_USBCMD);
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val &= ~EHCI_USBCMD_RUN;
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writel(val, op_reg_base + EHCI_USBCMD);
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wait_time = 2000;
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delta = 100;
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do {
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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udelay(delta);
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wait_time -= delta;
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
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break;
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}
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} while (wait_time > 0);
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}
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writel(0, op_reg_base + EHCI_USBINTR);
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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iounmap(base);
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return;
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}
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/*
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* handshake - spin reading a register until handshake completes
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* @ptr: address of hc register to be read
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* @mask: bits to look at in result of read
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* @done: value of those bits when handshake succeeds
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* @wait_usec: timeout in microseconds
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* @delay_usec: delay in microseconds to wait between polling
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*
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* Polls a register every delay_usec microseconds.
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* Returns 0 when the mask bits have the value done.
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* Returns -ETIMEDOUT if this condition is not true after
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* wait_usec microseconds have passed.
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*/
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static int handshake(void __iomem *ptr, u32 mask, u32 done,
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int wait_usec, int delay_usec)
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{
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u32 result;
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do {
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result = readl(ptr);
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result &= mask;
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if (result == done)
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return 0;
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udelay(delay_usec);
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wait_usec -= delay_usec;
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} while (wait_usec > 0);
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return -ETIMEDOUT;
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}
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/**
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* PCI Quirks for xHCI.
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*
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* Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
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* It signals to the BIOS that the OS wants control of the host controller,
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* and then waits 5 seconds for the BIOS to hand over control.
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* If we timeout, assume the BIOS is broken and take control anyway.
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*/
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static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
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{
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void __iomem *base;
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int ext_cap_offset;
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void __iomem *op_reg_base;
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u32 val;
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int timeout;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = ioremap_nocache(pci_resource_start(pdev, 0),
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pci_resource_len(pdev, 0));
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if (base == NULL)
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return;
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/*
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* Find the Legacy Support Capability register -
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* this is optional for xHCI host controllers.
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*/
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ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
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do {
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if (!ext_cap_offset)
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/* We've reached the end of the extended capabilities */
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goto hc_init;
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val = readl(base + ext_cap_offset);
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if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
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break;
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ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
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} while (1);
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/* If the BIOS owns the HC, signal that the OS wants it, and wait */
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if (val & XHCI_HC_BIOS_OWNED) {
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writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
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/* Wait for 5 seconds with 10 microsecond polling interval */
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timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
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0, 5000, 10);
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/* Assume a buggy BIOS and take HC ownership anyway */
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if (timeout) {
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dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
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" (BIOS bug ?) %08x\n", val);
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writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
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}
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}
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/* Disable any BIOS SMIs */
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writel(XHCI_LEGACY_DISABLE_SMI,
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base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
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hc_init:
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op_reg_base = base + XHCI_HC_LENGTH(readl(base));
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/* Wait for the host controller to be ready before writing any
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* operational or runtime registers. Wait 5 seconds and no more.
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*/
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timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
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5000, 10);
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/* Assume a buggy HC and start HC initialization anyway */
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if (timeout) {
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val = readl(op_reg_base + XHCI_STS_OFFSET);
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dev_warn(&pdev->dev,
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"xHCI HW not ready after 5 sec (HC bug?) "
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"status = 0x%x\n", val);
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}
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/* Send the halt and disable interrupts command */
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val = readl(op_reg_base + XHCI_CMD_OFFSET);
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val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
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writel(val, op_reg_base + XHCI_CMD_OFFSET);
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/* Wait for the HC to halt - poll every 125 usec (one microframe). */
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timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
|
|
XHCI_MAX_HALT_USEC, 125);
|
|
if (timeout) {
|
|
val = readl(op_reg_base + XHCI_STS_OFFSET);
|
|
dev_warn(&pdev->dev,
|
|
"xHCI HW did not halt within %d usec "
|
|
"status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
|
|
}
|
|
|
|
iounmap(base);
|
|
}
|
|
|
|
static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
|
|
{
|
|
if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
|
|
quirk_usb_handoff_uhci(pdev);
|
|
else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
|
|
quirk_usb_handoff_ohci(pdev);
|
|
else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
|
|
quirk_usb_disable_ehci(pdev);
|
|
else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
|
|
quirk_usb_handoff_xhci(pdev);
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
|