cc1338f259
When running on Xe_HP or beyond, let's use an updated format for describing topology in our error state dumps and debugfs to give a more accurate view of the hardware: - Just report DSS directly without the legacy "slice0" output that's no longer meaningful. - Indicate whether each DSS is accessible for geometry and/or compute. - Rename "rcs_topology" to "sseu_topology" since the information reported is common to both RCS and CCS engines now. v2: - Name static functions in a more consistent manner. (Lucas) Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220311225459.385515-2-matthew.d.roper@intel.com
149 lines
3.9 KiB
C
149 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_SSEU_H__
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#define __INTEL_SSEU_H__
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include "i915_gem.h"
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struct drm_i915_private;
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struct intel_gt;
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struct drm_printer;
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/*
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* Maximum number of slices on older platforms. Slices no longer exist
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* starting on Xe_HP ("gslices," "cslices," etc. are a different concept and
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* are not expressed through fusing).
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*/
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#define GEN_MAX_HSW_SLICES 3
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/*
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* Maximum number of subslices that can exist within a HSW-style slice. This
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* is only relevant to pre-Xe_HP platforms (Xe_HP and beyond use the
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* GEN_MAX_DSS value below).
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*/
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#define GEN_MAX_SS_PER_HSW_SLICE 6
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/* Maximum number of DSS on newer platforms (Xe_HP and beyond). */
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#define GEN_MAX_DSS 32
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/* Maximum number of EUs that can exist within a subslice or DSS. */
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#define GEN_MAX_EUS_PER_SS 16
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#define SSEU_MAX(a, b) ((a) > (b) ? (a) : (b))
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/* The maximum number of bits needed to express each subslice/DSS independently */
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#define GEN_SS_MASK_SIZE SSEU_MAX(GEN_MAX_DSS, \
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GEN_MAX_HSW_SLICES * GEN_MAX_SS_PER_HSW_SLICE)
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#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
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#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_SS_MASK_SIZE)
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#define GEN_MAX_EU_STRIDE GEN_SSEU_STRIDE(GEN_MAX_EUS_PER_SS)
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#define GEN_DSS_PER_GSLICE 4
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#define GEN_DSS_PER_CSLICE 8
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#define GEN_DSS_PER_MSLICE 8
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#define GEN_MAX_GSLICES (GEN_MAX_DSS / GEN_DSS_PER_GSLICE)
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#define GEN_MAX_CSLICES (GEN_MAX_DSS / GEN_DSS_PER_CSLICE)
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struct sseu_dev_info {
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u8 slice_mask;
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u8 subslice_mask[GEN_SS_MASK_SIZE];
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u8 geometry_subslice_mask[GEN_SS_MASK_SIZE];
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u8 compute_subslice_mask[GEN_SS_MASK_SIZE];
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u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE];
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u16 eu_total;
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u8 eu_per_subslice;
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u8 min_eu_in_pool;
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/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
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u8 subslice_7eu[3];
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u8 has_slice_pg:1;
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u8 has_subslice_pg:1;
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u8 has_eu_pg:1;
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/* Topology fields */
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u8 max_slices;
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u8 max_subslices;
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u8 max_eus_per_subslice;
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u8 ss_stride;
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u8 eu_stride;
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};
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/*
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* Powergating configuration for a particular (context,engine).
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*/
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struct intel_sseu {
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u8 slice_mask;
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u8 subslice_mask;
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u8 min_eus_per_subslice;
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u8 max_eus_per_subslice;
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};
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static inline struct intel_sseu
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intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
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{
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struct intel_sseu value = {
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.slice_mask = sseu->slice_mask,
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.subslice_mask = sseu->subslice_mask[0],
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.min_eus_per_subslice = sseu->max_eus_per_subslice,
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.max_eus_per_subslice = sseu->max_eus_per_subslice,
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};
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return value;
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}
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static inline bool
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intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
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int subslice)
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{
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u8 mask;
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int ss_idx = subslice / BITS_PER_BYTE;
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if (slice >= sseu->max_slices ||
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subslice >= sseu->max_subslices)
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return false;
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GEM_BUG_ON(ss_idx >= sseu->ss_stride);
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mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
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return mask & BIT(subslice % BITS_PER_BYTE);
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}
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void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
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u8 max_subslices, u8 max_eus_per_subslice);
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unsigned int
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intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
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unsigned int
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intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
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u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
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u32 intel_sseu_get_compute_subslices(const struct sseu_dev_info *sseu);
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void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
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u8 *subslice_mask, u32 ss_mask);
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void intel_sseu_info_init(struct intel_gt *gt);
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u32 intel_sseu_make_rpcs(struct intel_gt *gt,
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const struct intel_sseu *req_sseu);
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void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p);
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void intel_sseu_print_topology(struct drm_i915_private *i915,
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const struct sseu_dev_info *sseu,
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struct drm_printer *p);
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u16 intel_slicemask_from_dssmask(u64 dss_mask, int dss_per_slice);
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#endif /* __INTEL_SSEU_H__ */
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