56d428ae1c
* Support for handling misaligned accesses in S-mode. * Probing for misaligned access support is now properly cached and handled in parallel. * PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions. * Performance improvements for TLB flushing. * Support for many new relocations in the module loader. * Various bug fixes and cleanups. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmVOUCcTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYicJ2D/9S+9dnHYHVGTeJfr9Zf2T4r+qHBPyx LXbTAbgHN6139MgcRLMRlcUaQ04RVxuBCWhxewJ6mQiHiYNlullgKmJO8oYMS4uZ 2yQGHKhzKEVluXxe+qT6VW+zsP0cY6pDQ+e59AqZgyWzvATxMU4VtFfCDdjFG03I k/8Y3MUKSHAKzIHUsGHiMW5J2YRiM/iVehv2gZfanreulWlK6lyiV4AZ4KChu8Sa gix9QkFJw+9+7RHnouHvczt4xTqLPJQcdecLJsbisEI4VaaPtTVzkvXx/kwbMwX0 qkQnZ7I60fPHrCb9ccuedjDMa1Z0lrfwRldBGz9f9QaW37Eppirn6LA5JiZ1cA47 wKTwba6gZJCTRXELFTJLcv+Cwdy003E0y3iL5UK2rkbLqcxfvLdq1WAJU2t05Lmh aRQN10BtM2DZG+SNPlLoBpXPDw0Q3KOc20zGtuhmk010+X4yOK7WXlu8zNGLLE0+ yHamiZqAbpIUIEzwDdGbb95jywR1sUhNTbScuhj4Rc79ZqLtPxty1PUhnfqFat1R i3ngQtCbeUUYFS2YV9tKkXjLf/xkQNRbt7kQBowuvFuvfksl9UwMdRAWcE/h0M9P 7uz7cBFhuG0v/XblB7bUhYLkKITvP+ltSMyxaGlfpGqCLAH2KIztdZ2PLWLRdKeU +9dtZSQR6oBLqQ== =NhdR -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for handling misaligned accesses in S-mode - Probing for misaligned access support is now properly cached and handled in parallel - PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions - Performance improvements for TLB flushing - Support for many new relocations in the module loader - Various bug fixes and cleanups * tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) riscv: Optimize bitops with Zbb extension riscv: Rearrange hwcap.h and cpufeature.h drivers: perf: Do not broadcast to other cpus when starting a counter drivers: perf: Check find_first_bit() return value of: property: Add fw_devlink support for msi-parent RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings riscv: Don't use PGD entries for the linear mapping RISC-V: Probe misaligned access speed in parallel RISC-V: Remove __init on unaligned_emulation_finish() RISC-V: Show accurate per-hart isa in /proc/cpuinfo RISC-V: Don't rely on positional structure initialization riscv: Add tests for riscv module loading riscv: Add remaining module relocations riscv: Avoid unaligned access when relocating modules riscv: split cache ops out of dma-noncoherent.c riscv: Improve flush_tlb_kernel_range() riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: Improve flush_tlb_range() for hugetlb pages riscv: Improve tlb_flush() ...
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.. SPDX-License-Identifier: GPL-2.0
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RISC-V Linux User ABI
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=====================
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ISA string ordering in /proc/cpuinfo
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------------------------------------
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The canonical order of ISA extension names in the ISA string is defined in
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chapter 27 of the unprivileged specification.
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The specification uses vague wording, such as should, when it comes to ordering,
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so for our purposes the following rules apply:
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#. Single-letter extensions come first, in canonical order.
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The canonical order is "IMAFDQLCBKJTPVH".
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#. All multi-letter extensions will be separated from other extensions by an
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underscore.
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#. Additional standard extensions (starting with 'Z') will be sorted after
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single-letter extensions and before any higher-privileged extensions.
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#. For additional standard extensions, the first letter following the 'Z'
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conventionally indicates the most closely related alphabetical
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extension category. If multiple 'Z' extensions are named, they will be
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ordered first by category, in canonical order, as listed above, then
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alphabetically within a category.
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#. Standard supervisor-level extensions (starting with 'S') will be listed
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after standard unprivileged extensions. If multiple supervisor-level
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extensions are listed, they will be ordered alphabetically.
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#. Standard machine-level extensions (starting with 'Zxm') will be listed
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after any lower-privileged, standard extensions. If multiple machine-level
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extensions are listed, they will be ordered alphabetically.
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#. Non-standard extensions (starting with 'X') will be listed after all standard
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extensions. If multiple non-standard extensions are listed, they will be
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ordered alphabetically.
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An example string following the order is::
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rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
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"isa" and "hart isa" lines in /proc/cpuinfo
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-------------------------------------------
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The "isa" line in /proc/cpuinfo describes the lowest common denominator of
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RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
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"hart isa" line, in contrast, describes the set of extensions recognized by the
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kernel on the particular hart being described, even if those extensions may not
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be present on all harts in the system.
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In both lines, the presence of an extension guarantees only that the hardware
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has the described capability. Additional kernel support or policy changes may be
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required before an extension's capability is fully usable by userspace programs.
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Similarly, for S-mode extensions, presence in one of these lines does not
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guarantee that the kernel is taking advantage of the extension, or that the
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feature will be visible in guest VMs managed by this kernel.
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Inversely, the absence of an extension in these lines does not necessarily mean
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the hardware does not support that feature. The running kernel may not recognize
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the extension, or may have deliberately removed it from the listing.
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Misaligned accesses
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-------------------
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Misaligned accesses are supported in userspace, but they may perform poorly.
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