18aecc2b64
This support was partially present in the existing code (look for "__tilegx__" ifdefs) but with this change you can build a working kernel using the TILE-Gx toolchain and ARCH=tilegx. Most of these files are new, generally adding a foo_64.c file where previously there was just a foo_32.c file. The ARCH=tilegx directive redirects to arch/tile, not arch/tilegx, using the existing SRCARCH mechanism in the top-level Makefile. Changes to existing files: - <asm/bitops.h> and <asm/bitops_32.h> changed to factor the include of <asm-generic/bitops/non-atomic.h> in the common header. - <asm/compat.h> and arch/tile/kernel/compat.c changed to remove the "const" markers I had put on compat_sys_execve() when trying to match some recent similar changes to the non-compat execve. It turns out the compat version wasn't "upgraded" to use const. - <asm/opcode-tile_64.h> and <asm/opcode_constants_64.h> were previously included accidentally, with the 32-bit contents. Now they have the proper 64-bit contents. Finally, I had to hack the existing hacky drivers/input/input-compat.h to add yet another "#ifdef" for INPUT_COMPAT_TEST (same as x86_64). Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> [drivers/input]
162 lines
4.4 KiB
C
162 lines
4.4 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#ifndef _ASM_TILE_SPINLOCK_64_H
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#define _ASM_TILE_SPINLOCK_64_H
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/* Shifts and masks for the various fields in "lock". */
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#define __ARCH_SPIN_CURRENT_SHIFT 17
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#define __ARCH_SPIN_NEXT_MASK 0x7fff
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#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
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/*
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* Return the "current" portion of a ticket lock value,
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* i.e. the number that currently owns the lock.
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*/
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static inline int arch_spin_current(u32 val)
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{
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return val >> __ARCH_SPIN_CURRENT_SHIFT;
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}
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/*
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* Return the "next" portion of a ticket lock value,
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* i.e. the number that the next task to try to acquire the lock will get.
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*/
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static inline int arch_spin_next(u32 val)
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{
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return val & __ARCH_SPIN_NEXT_MASK;
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}
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/* The lock is locked if a task would have to wait to get it. */
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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u32 val = lock->lock;
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return arch_spin_current(val) != arch_spin_next(val);
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}
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/* Bump the current ticket so the next task owns the lock. */
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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wmb(); /* guarantee anything modified under the lock is visible */
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__insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
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}
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void arch_spin_unlock_wait(arch_spinlock_t *lock);
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void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
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/* Grab the "next" ticket number and bump it atomically.
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* If the current ticket is not ours, go to the slow path.
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* We also take the slow path if the "next" value overflows.
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*/
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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u32 val = __insn_fetchadd4(&lock->lock, 1);
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u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
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if (unlikely(arch_spin_current(val) != ticket))
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arch_spin_lock_slow(lock, ticket);
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}
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/* Try to get the lock, and return whether we succeeded. */
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int arch_spin_trylock(arch_spinlock_t *lock);
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/* We cannot take an interrupt after getting a ticket, so don't enable them. */
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* We use fetchadd() for readers, and fetchor() with the sign bit
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* for writers.
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*/
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#define __WRITE_LOCK_BIT (1 << 31)
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static inline int arch_write_val_locked(int val)
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{
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return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
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}
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int arch_read_can_lock(arch_rwlock_t *rw)
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{
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return !arch_write_val_locked(rw->lock);
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}
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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static inline int arch_write_can_lock(arch_rwlock_t *rw)
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{
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return rw->lock == 0;
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}
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extern void __read_lock_failed(arch_rwlock_t *rw);
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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u32 val = __insn_fetchaddgez4(&rw->lock, 1);
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if (unlikely(arch_write_val_locked(val)))
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__read_lock_failed(rw);
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}
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extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
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if (unlikely(val != 0))
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__write_lock_failed(rw, val);
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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__insn_mf();
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__insn_fetchadd4(&rw->lock, -1);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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__insn_mf();
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rw->lock = 0;
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
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if (likely(val == 0))
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return 1;
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if (!arch_write_val_locked(val))
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__insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
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return 0;
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}
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#endif /* _ASM_TILE_SPINLOCK_64_H */
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