90b6c5c73c
This flag was historically used to indicate that a clk is a "basic" type of clk like a mux, divider, gate, etc. This never turned out to be very useful though because it was hard to cleanly split "basic" clks from other clks in a system. This one flag was a way for type introspection and it just didn't scale. If anything, it was used by the TI clk driver to indicate that a clk_hw wasn't contained in the SoC specific clk structure. We can get rid of this define now that TI is finding those clks a different way. Cc: Tero Kristo <t-kristo@ti.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@mips.com> Cc: James Hogan <jhogan@kernel.org> Cc: <linux-mips@vger.kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: <linux-pwm@vger.kernel.org> Cc: <linux-amlogic@lists.infradead.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
131 lines
2.9 KiB
C
131 lines
2.9 KiB
C
/*
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* mmp gate clock operation source file
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*
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* Copyright (C) 2014 Marvell
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* Chao Xie <chao.xie@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include "clk.h"
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/*
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* Some clocks will have mutiple bits to enable the clocks, and
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* the bits to disable the clock is not same as enabling bits.
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*/
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#define to_clk_mmp_gate(hw) container_of(hw, struct mmp_clk_gate, hw)
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static int mmp_clk_gate_enable(struct clk_hw *hw)
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{
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struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
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unsigned long flags = 0;
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unsigned long rate;
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u32 tmp;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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tmp = readl(gate->reg);
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tmp &= ~gate->mask;
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tmp |= gate->val_enable;
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writel(tmp, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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if (gate->flags & MMP_CLK_GATE_NEED_DELAY) {
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rate = clk_hw_get_rate(hw);
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/* Need delay 2 cycles. */
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udelay(2000000/rate);
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}
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return 0;
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}
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static void mmp_clk_gate_disable(struct clk_hw *hw)
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{
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struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
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unsigned long flags = 0;
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u32 tmp;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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tmp = readl(gate->reg);
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tmp &= ~gate->mask;
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tmp |= gate->val_disable;
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writel(tmp, gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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}
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static int mmp_clk_gate_is_enabled(struct clk_hw *hw)
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{
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struct mmp_clk_gate *gate = to_clk_mmp_gate(hw);
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unsigned long flags = 0;
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u32 tmp;
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if (gate->lock)
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spin_lock_irqsave(gate->lock, flags);
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tmp = readl(gate->reg);
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if (gate->lock)
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spin_unlock_irqrestore(gate->lock, flags);
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return (tmp & gate->mask) == gate->val_enable;
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}
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const struct clk_ops mmp_clk_gate_ops = {
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.enable = mmp_clk_gate_enable,
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.disable = mmp_clk_gate_disable,
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.is_enabled = mmp_clk_gate_is_enabled,
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};
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struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u32 mask, u32 val_enable, u32 val_disable,
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unsigned int gate_flags, spinlock_t *lock)
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{
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struct mmp_clk_gate *gate;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &mmp_clk_gate_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_gate assignments */
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gate->reg = reg;
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gate->mask = mask;
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gate->val_enable = val_enable;
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gate->val_disable = val_disable;
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gate->flags = gate_flags;
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gate->lock = lock;
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gate->hw.init = &init;
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clk = clk_register(dev, &gate->hw);
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if (IS_ERR(clk))
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kfree(gate);
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return clk;
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}
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