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When 96KHz sample rate is used, and MCLK is 24.576MHz, we will need
pll_in = 24576000 and pll_out = 49152000 which is not supported by
RT5682S_PLL2. Use RT5682S_PLL1 in this case.
We don't test sample rate because RT5682S_PLL2 doesn't support 24.576MHz
input and in the MCLK = 24.576MHz, sample rate = 48KHz case, i.e.
pll_in == pll_out, PLL will not be used at all.
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20240411220347.131267-13-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
dcc2cd8000