Dan Williams 14d7887407 cxl/mem: Consolidate CXL DVSEC Range enumeration in the core ...

In preparation for fixing the setting of the 'mem_enabled' bit in CXL
DVSEC Control register, move all CXL DVSEC range enumeration into the
same source file.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165291688886.1426646.15046138604010482084.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

2022-05-19 08:50:41 -07:00

..

test

cxl/mem: Consolidate CXL DVSEC Range enumeration in the core

2022-05-19 08:50:41 -07:00

config_check.c

tools/testing/cxl: Introduce a mocked-up CXL port hierarchy

2021-09-21 13:47:10 -07:00

Kbuild

cxl/mem: Consolidate CXL DVSEC Range enumeration in the core

2022-05-19 08:50:41 -07:00

mock_acpi.c

cxl/core: Generalize dport enumeration in the core

2022-02-08 22:57:30 -08:00

mock_mem.c

cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()

2022-04-12 19:11:58 -07:00