de1835e3b5
Convert the NVIDIA Tegra pinmux controller bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
90 lines
2.4 KiB
YAML
90 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra194 Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra194-pinmux
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reg:
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items:
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- description: APB_MISC_GP_*_PADCTRL registers (pad control)
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- description: PINMUX_AUX_* registers (pinmux)
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patternProperties:
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"^pinmux(-[a-z0-9-_]+)?$":
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type: object
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properties:
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phandle: true
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra-pinmux-common.yaml
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additionalProperties: false
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properties:
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nvidia,pins:
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description: An array of strings. Each string contains the name of a
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pin or group. Valid values for these names are listed below.
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Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins are
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part of PCIE C5 power partition. Client devices must enable this
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partition before accessing the configuration for these pins.
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items:
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enum: [ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
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# drive groups
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drive_pex_l5_clkreq_n_pgg0, drive_pex_l5_rst_n_pgg1 ]
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nvidia,function:
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enum: [ pe5 ]
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nvidia,pull: true
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nvidia,tristate: true
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nvidia,schmitt: true
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nvidia,enable-input: true
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nvidia,open-drain: true
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nvidia,lock: true
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nvidia,drive-type: true
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nvidia,io-hv: true
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required:
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- nvidia,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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examples:
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- |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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pinmux@2430000 {
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compatible = "nvidia,tegra194-pinmux";
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reg = <0x2430000 0x17000>,
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<0xc300000 0x04000>;
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pinctrl-names = "pex_rst";
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pinctrl-0 = <&pex_rst_c5_out_state>;
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pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
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pex_rst {
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nvidia,pins = "pex_l5_rst_n_pgg1";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_ENABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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};
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...
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