Andi Kleen de4218634e x86: implement support to synchronize RDTSC through MFENCE on AMD CPUs
According to AMD RDTSC can be synchronized through MFENCE.
Implement the necessary CPUID bit for that.

Cc: andreas.herrmann3@amd.com
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-01-30 13:32:37 +01:00
..
2008-01-30 13:32:31 +01:00
2008-01-30 13:32:31 +01:00
2007-10-20 01:13:56 +02:00
2007-10-17 20:16:15 +02:00
2007-10-20 01:13:56 +02:00
2008-01-30 13:30:35 +01:00
2008-01-30 13:32:36 +01:00
2008-01-30 13:32:00 +01:00
2008-01-30 13:32:32 +01:00
2007-10-11 11:16:56 +02:00
2008-01-30 13:32:32 +01:00