Jani Nikula e01163e82b drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b
There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.

v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper

Bspec: 54128
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/a2902cc188973f022f282f2a77e693afdecefb5a.1631191763.git.jani.nikula@intel.com
2021-09-20 18:47:00 +03:00
..
2021-09-10 11:22:23 -07:00
2021-07-30 14:52:00 +10:00
2021-08-10 20:14:01 +02:00
2021-09-01 11:26:46 -07:00
2021-09-01 11:26:46 -07:00
2021-07-21 11:58:28 +10:00
2021-07-30 14:52:00 +10:00
2021-09-01 11:26:46 -07:00
2021-09-01 11:26:46 -07:00
2021-08-10 20:14:01 +02:00
2021-09-03 15:33:47 -07:00
2021-09-01 11:26:46 -07:00
2021-07-21 11:58:28 +10:00
2021-08-10 20:14:01 +02:00
2021-07-30 14:52:00 +10:00
2021-08-26 13:05:19 +10:00
2021-09-10 11:22:23 -07:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-05-17 21:19:48 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-19 09:02:55 +09:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-07-05 08:54:44 +02:00