Vidya Sagar 0983529d75 phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration ... Set ENABLE_L2_EXIT_RATE_CHANGE register bit to request UPHY PLL rate change to Gen1 during initialization. This helps in the below surprise link down cases, - Surprise link down happens at Gen3/Gen4 link speed. - Surprise link down happens and external REFCLK is cut off, which causes UPHY PLL rate to deviate to an invalid rate. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20221013183854.21087-9-vidyas@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>		2022-10-28 17:43:12 +05:30
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Kconfig	phy: tegra: Select USB_COMMON for usb_get_maximum_speed()	2020-04-16 15:05:53 +02:00
Makefile	phy: tegra: xusb: Add Tegra194 support	2020-03-19 13:59:46 +01:00
phy-tegra194-p2u.c	phy: tegra: p2u: Set ENABLE_L2_EXIT_RATE_CHANGE in calibration	2022-10-28 17:43:12 +05:30
xusb-tegra124.c	phy: tegra: Don't use device-managed API to allocate ports	2020-03-19 14:00:05 +01:00
xusb-tegra186.c	USB/Thunderbolt changes for 6.1-rc1	2022-10-07 16:48:26 -07:00
xusb-tegra210.c	phy: tegra: xusb: Tegra210 host mode VBUS control	2021-06-03 14:52:45 +02:00
xusb.c	USB/Thunderbolt changes for 6.1-rc1	2022-10-07 16:48:26 -07:00
xusb.h	phy: tegra: xusb: add utmi pad power on/down ops	2022-08-19 11:10:08 +02:00